DS008-1.1-JUN03

CYGNAL Integrated Products, Inc.

Page 1

Preliminary

High-Speed Mixed-Signal ISP FLASH MCU

C8051F120/1/2/3
C8051F124/5/6/7

ANALOG PERIPHERALS
-

SAR ADC

12-Bit (C8051F120/1/4/5)

10-Bit (C8051F122/3/6/7)

± 1 LSB I NL

Programmable Throughput up to 100 ksps

Up to 8 External Inputs; Programmable as Single-Ended or
Differential

Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5

Data-Dependent Windowed Interrupt Generator

Built-in Temperature Sensor

8-bit ADC

Programmable Throughput up to 500 ksps

8 External Inputs (Single-Ended or Differential)

Programmable Amplifier Gain: 4, 2, 1, 0.5

Two 12-bit DACs

Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation

Two Analog Comparators

Voltage Reference

VDD Monitor/Brown-Out Detector

ON-CHIP JTAG DEBUG & BOUNDARY SCAN
-

On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging

Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers

Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets

IEEE1149.1 Compliant Boundary Scan

Complete Development Kit

HIGH SPEED 8051

µC CORE

Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks

Up to 100 MIPS (C8051F120/1/2/3) or 50 MIPS
(C8051F124/5/6/7) Throughput using Integrated PLL

2-cycle 16 x 16 MAC Engine (C8051F120/1/2/3)

Flexible Interrupt Sources

MEMORY
-

8448 Bytes Internal Data RAM (8k + 256)

128k Bytes Banked FLASH; In-System programmable in
1024-byte Sectors

External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)

DIGITAL PERIPHERALS
-

8 Byte-Wide Port I/O (C8051F120/2/4/6); 5V tolerant

4 Byte-Wide Port I/O (C8051F121/3/5/7); 5V tolerant

Hardware SMBusTM (I

CTM Compatible), SPITM, and

Two UART Serial Ports Available Concurrently

Programmable 16-bit Counter/Timer Array with
6 Capture/Compare Modules

5 General Purpose 16-bit Counter/Timers

Dedicated Watch-Dog Timer; Bi-directional Reset Pin

CLOCK SOURCES
-

Internal Precision Oscillator: 24.5 MHz

Flexible PLL technology

External Oscillator: Crystal, RC, C, or Clock

POWER SUPPLIES
-

Supply Range: 2.7-3.6V (50 MIPS) 3.0-3.6V (100 MIPS)

Power Saving Sleep and Shutdown Modes

100-PINTQFP OR 64-PINTQFP PACKAGING
-

Temperature Range: -40°C to +85°C

JTAG

128KB

ISP FLASH

8448 B

SRAM

16 x 16 MAC

('F120/1/2/3)

10/12-bit

100ksps

ADC

CLOCK / PLL

CIRCUIT

PGA

VREF

12-Bit

DAC

TEMP

SENSOR

VOLTAGE

COMPARATORS

ANALOG PERIPHERALS

Port0

Port1

Port2

Port3

OSSBAR

DIGITAL I/O

HIGH-SPEED CONTROLLER CORE

DEBUG

CIRCUITRY

INTERRUPTS

8051 CPU

(50 or 100MIPS)

12-Bit

DAC

8-bit

500ksps

ADC

Port 4

Port 5

Port 6

Port 7

Exte

r
na

I
nte

r
f
a

100 pin

64 pin

PGA

UART0

SMBus

SPI Bus

PCA

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

UART1

DS008-1.1-JUN03

Page 3

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

TABLE OF CONTENTS

1. SYSTEM OVERVIEW .........................................................................................................19

1.1. CIP-51TM Microcontroller Core ......................................................................................25

1.1.1. Fully 8051 Compatible ..........................................................................................25
1.1.2. Improved Throughput ............................................................................................25
1.1.3. Additional Features................................................................................................26

1.2. On-Chip Memory ............................................................................................................27
1.3. JTAG Debug and Boundary Scan ...................................................................................28
1.4. 16 x 16 MAC (Multiply and Accumulate) Engine..........................................................29
1.5. Programmable Digital I/O and Crossbar .........................................................................30
1.6. Programmable Counter Array .........................................................................................31
1.7. Serial Ports.......................................................................................................................32
1.8. 12-Bit Analog to Digital Converter .................................................................................33
1.9. 8-Bit Analog to Digital Converter ...................................................................................34
1.10. Comparators and DACs...................................................................................................35

2. ABSOLUTE MAXIMUM RATINGS ..................................................................................36
3. GLOBAL DC ELECTRICAL CHARACTERISTICS ......................................................37
4. PINOUT AND PACKAGE DEFINITIONS........................................................................39
5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) ..................................................................49

5.1. Analog Multiplexer and PGA..........................................................................................49
5.2. ADC Modes of Operation ...............................................................................................51

5.2.1. Starting a Conversion.............................................................................................51
5.2.2. Tracking Modes .....................................................................................................52
5.2.3. Settling Time Requirements ..................................................................................53

5.3. ADC0 Programmable Window Detector.........................................................................60

6. ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY) ..................................................................67

6.1. Analog Multiplexer and PGA..........................................................................................67
6.2. ADC Modes of Operation ...............................................................................................69

6.2.1. Starting a Conversion.............................................................................................69
6.2.2. Tracking Modes .....................................................................................................70
6.2.3. Settling Time Requirements ..................................................................................71

6.3. ADC0 Programmable Window Detector.........................................................................78

7. ADC2 (8-BIT ADC) ...............................................................................................................85

7.1. Analog Multiplexer and PGA..........................................................................................85
7.2. ADC2 Modes of Operation .............................................................................................86

7.2.1. Starting a Conversion.............................................................................................86
7.2.2. Tracking Modes .....................................................................................................86
7.2.3. Settling Time Requirements ..................................................................................88

7.3. ADC2 Programmable Window Detector.........................................................................94

7.3.1. Window Detector In Single-Ended Mode .............................................................94
7.3.2. Window Detector In Differential Mode.................................................................95

8. DACS, 12-BIT VOLTAGE MODE ......................................................................................99

8.1. DAC Output Scheduling..................................................................................................99

Page 4

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

8.1.1. Update Output On-Demand ...................................................................................99
8.1.2. Update Output Based on Timer Overflow ...........................................................100

8.2. DAC Output Scaling/Justification.................................................................................100

9. VOLTAGE REFERENCE (C8051F120/2/4/6) .................................................................107
10. VOLTAGE REFERENCE (C8051F121/3/5/7) .................................................................109
11. COMPARATORS................................................................................................................111
12. CIP-51 MICROCONTROLLER........................................................................................119

12.1. Instruction Set................................................................................................................120

12.1.1. Instruction and CPU Timing................................................................................120
12.1.2. MOVX Instruction and Program Memory...........................................................120

12.2. Memory Organization ...................................................................................................125

12.2.1. Program Memory .................................................................................................125
12.2.2. Data Memory .......................................................................................................127
12.2.3. General Purpose Registers ...................................................................................127
12.2.4. Bit Addressable Locations ...................................................................................127
12.2.5. Stack

.................................................................................................................127

12.2.6. Special Function Registers...................................................................................128

12.2.6.1. SFR Paging..................................................................................................128
12.2.6.2. Interrupts and SFR Paging...........................................................................128
12.2.6.3. SFR Page Stack Example ............................................................................130

12.2.7. Register Descriptions ...........................................................................................143

12.3. Interrupt Handler ...........................................................................................................146

12.3.1. MCU Interrupt Sources and Vectors ...................................................................146
12.3.2. External Interrupts ...............................................................................................146
12.3.3. Interrupt Priorities................................................................................................148
12.3.4. Interrupt Latency..................................................................................................148
12.3.5. Interrupt Register Descriptions ............................................................................149

12.4. Power Management Modes ...........................................................................................155

12.4.1. Idle Mode .............................................................................................................155
12.4.2. Stop Mode............................................................................................................155

13. MULTIPLY AND ACCUMULATE (MAC0) ...................................................................157

13.1. Special Function Registers ............................................................................................157
13.2. Integer and Fractional Math ..........................................................................................158
13.3. Operating in Multiply and Accumulate Mode...............................................................159
13.4. Operating in Multiply Only Mode.................................................................................159
13.5. Accumulator Shift Operations .......................................................................................159
13.6. Rounding and Saturation ...............................................................................................160
13.7. Usage Examples ............................................................................................................160

14. RESET SOURCES ..............................................................................................................167

14.1. Power-on Reset..............................................................................................................168
14.2. Power-fail Reset ............................................................................................................168
14.3. External Reset................................................................................................................168
14.4. Missing Clock Detector Reset .......................................................................................169
14.5. Comparator0 Reset ........................................................................................................169
14.6. External CNVSTR0 Pin Reset.......................................................................................169

DS008-1.1-JUN03

Page 5

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

14.7. Watchdog Timer Reset ..................................................................................................169

14.7.1. Enable/Reset WDT ..............................................................................................169
14.7.2. Disable WDT .......................................................................................................170
14.7.3. Disable WDT Lockout.........................................................................................170
14.7.4. Setting WDT Interval...........................................................................................170

15. OSCILLATORS...................................................................................................................173

15.1. Programmable Internal Oscillator .................................................................................173
15.2. External Oscillator Drive Circuit...................................................................................175
15.3. System Clock Selection.................................................................................................175
15.4. External Crystal Example..............................................................................................177
15.5. External RC Example ....................................................................................................177
15.6. External Capacitor Example..........................................................................................177
15.7. Phase-Locked Loop (PLL) ............................................................................................178

15.7.1. PLL Input Clock and Pre-divider.........................................................................178
15.7.2. PLL Multiplication and Output Clock .................................................................178
15.7.3. Powering on and Initializing the PLL..................................................................179

16. FLASH MEMORY ..............................................................................................................185

16.1. Programming The Flash Memory .................................................................................185

16.1.1. Non-volatile Data Storage ...................................................................................185
16.1.2. Erasing FLASH Pages From Software ................................................................186
16.1.3. Writing FLASH Memory From Software ...........................................................187

16.2. Security Options ............................................................................................................188

17. BRANCH TARGET CACHE.............................................................................................193

17.1. Cache and Prefetch Operation .......................................................................................193
17.2. Cache and Prefetch Optimization ..................................................................................194

18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................199

18.1. Accessing XRAM..........................................................................................................199

18.1.1. 16-Bit MOVX Example.......................................................................................199
18.1.2. 8-Bit MOVX Example.........................................................................................199

18.2. Configuring the External Memory Interface .................................................................199
18.3. Port Selection and Configuration ..................................................................................200
18.4. Multiplexed and Non-multiplexed Selection.................................................................202

18.4.1. Multiplexed Configuration ..................................................................................202
18.4.2. Non-multiplexed Configuration...........................................................................203

18.5. Memory Mode Selection ...............................................................................................204

18.5.1. Internal XRAM Only ...........................................................................................204
18.5.2. Split Mode without Bank Select ..........................................................................204
18.5.3. Split Mode with Bank Select ...............................................................................205
18.5.4. External Only .......................................................................................................205

18.6. Timing

.......................................................................................................................206

18.6.1. Non-multiplexed Mode........................................................................................207

18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = `101', `110', or `111'................................207
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = `101' or `111'............208
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = `110'. ..............................209

18.6.2. Multiplexed Mode................................................................................................210

Page 6

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = `001', `010', or `011'................................210
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = `001' or `011'............211
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = `010'. ..............................212

19. PORT INPUT/OUTPUT .....................................................................................................215

19.1. Ports 0 through 3 and the Priority Crossbar Decoder....................................................217

19.1.1. Crossbar Pin Assignment and Allocation ............................................................217
19.1.2. Configuring the Output Modes of the Port Pins ..................................................218
19.1.3. Configuring Port Pins as Digital Inputs ...............................................................219
19.1.4. Weak Pull-ups......................................................................................................219
19.1.5. Configuring Port 1 Pins as Analog Inputs ...........................................................219
19.1.6. External Memory Interface Pin Assignments ......................................................220
19.1.7. Crossbar Pin Assignment Example......................................................................222

19.2. Ports 4 through 7 (C8051F120/2/4/6 only) ...................................................................231

19.2.1. Configuring Ports which are not Pinned Out.......................................................231
19.2.2. Configuring the Output Modes of the Port Pins ..................................................231
19.2.3. Configuring Port Pins as Digital Inputs ...............................................................232
19.2.4. Weak Pull-ups......................................................................................................232
19.2.5. External Memory Interface ..................................................................................232

20. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................237

20.1. Supporting Documents ..................................................................................................238
20.2. SMBus Protocol.............................................................................................................238

20.2.1. Arbitration............................................................................................................239
20.2.2. Clock Low Extension...........................................................................................239
20.2.3. SCL Low Timeout ...............................................................................................239
20.2.4. SCL High (SMBus Free) Timeout.......................................................................239

20.3. SMBus Transfer Modes.................................................................................................240

20.3.1. Master Transmitter Mode ....................................................................................240
20.3.2. Master Receiver Mode.........................................................................................240
20.3.3. Slave Transmitter Mode.......................................................................................241
20.3.4. Slave Receiver Mode ...........................................................................................241

20.4. SMBus Special Function Registers ...............................................................................242

20.4.1. Control Register ...................................................................................................242
20.4.2. Clock Rate Register .............................................................................................244
20.4.3. Data Register........................................................................................................245
20.4.4. Address Register ..................................................................................................245
20.4.5. Status Register .....................................................................................................246

21. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................249

21.1. Signal Descriptions........................................................................................................250

21.1.1. Master Out, Slave In (MOSI) ..............................................................................250
21.1.2. Master In, Slave Out (MISO) ..............................................................................250
21.1.3. Serial Clock (SCK) ..............................................................................................250
21.1.4. Slave Select (NSS)...............................................................................................250

21.2. SPI0 Master Mode Operation........................................................................................251
21.3. SPI0 Slave Mode Operation ..........................................................................................253
21.4. SPI0 Interrupt Sources...................................................................................................253

DS008-1.1-JUN03

Page 7

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

21.5. Serial Clock Timing ......................................................................................................254
21.6. SPISpecial Function Registers .....................................................................................256

22. UART0 ..................................................................................................................................263

22.1. UART0 Operational Modes ..........................................................................................264

22.1.1. Mode 0: Synchronous Mode................................................................................264
22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................265
22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................266
22.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................267

22.2. Multiprocessor Communications...................................................................................268

22.2.1. Configuration of a Masked Address ....................................................................268
22.2.2. Broadcast Addressing ..........................................................................................268

22.3. Frame and Transmission Error Detection......................................................................269

23. UART1 ..................................................................................................................................275

23.1. Enhanced Baud Rate Generation...................................................................................276
23.2. Operational Modes ........................................................................................................277

23.2.1. 8-Bit UART .........................................................................................................277
23.2.2. 9-Bit UART .........................................................................................................278

23.3. Multiprocessor Communications...................................................................................279

24. TIMERS................................................................................................................................285

24.1. Timer 0 and Timer 1......................................................................................................285

24.1.1. Mode 0: 13-bit Counter/Timer.............................................................................285
24.1.2. Mode 1: 16-bit Counter/Timer.............................................................................286
24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload .................................................287
24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................288

24.2. Timer 2, Timer 3, and Timer 4 ......................................................................................293

24.2.1. Configuring Timer 2, 3, and 4 to Count Down....................................................293
24.2.2. Capture Mode ......................................................................................................294
24.2.3. Auto-Reload Mode ..............................................................................................295
24.2.4. Toggle Output Mode (Timer 2 and Timer 4 Only)..............................................295

25. PROGRAMMABLE COUNTER ARRAY .......................................................................301

25.1. PCA Counter/Timer.......................................................................................................302
25.2. Capture/Compare Modules............................................................................................303

25.2.1. Edge-triggered Capture Mode .............................................................................304
25.2.2. Software Timer (Compare) Mode........................................................................305
25.2.3. High Speed Output Mode ....................................................................................306
25.2.4. Frequency Output Mode ......................................................................................307
25.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................308
25.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................309

25.3. Register Descriptions for PCA0 ....................................................................................310

26. JTAG (IEEE 1149.1)............................................................................................................315

26.1. Boundary Scan...............................................................................................................316

26.1.1. EXTEST Instruction ............................................................................................317
26.1.2. SAMPLE Instruction ...........................................................................................317
26.1.3. BYPASS Instruction ............................................................................................317
26.1.4. IDCODE Instruction ............................................................................................317

DS008-1.1-JUN03

Page 9

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

LIST OF FIGURES

1. SYSTEM OVERVIEW .........................................................................................................19

Figure 1.1. C8051F120/124 Block Diagram..........................................................................21
Figure 1.2. C8051F121/125 Block Diagram..........................................................................22
Figure 1.3. C8051F122/126 Block Diagram..........................................................................23
Figure 1.4. C8051F123/127 Block Diagram..........................................................................24
Figure 1.5. On-Board Clock and Reset ..................................................................................26
Figure 1.6. On-Chip Memory Map ........................................................................................27
Figure 1.7. Development/In-System Debug Diagram ...........................................................28
Figure 1.8. MAC0 Block Diagram ........................................................................................29
Figure 1.9. Digital Crossbar Diagram....................................................................................30
Figure 1.10. PCA Block Diagram............................................................................................31
Figure 1.11. 12-Bit ADC Block Diagram................................................................................33
Figure 1.12. 8-Bit ADC Diagram ............................................................................................34
Figure 1.13. Comparator and DAC Diagram...........................................................................35

Figure 4.1. TQFP-100 Pinout Diagram..................................................................................44
Figure 4.2. TQFP-100 Package Drawing...............................................................................45
Figure 4.3. TQFP-64 Pinout Diagram....................................................................................46
Figure 4.4. TQFP-64 Package Drawing.................................................................................47

5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) ..................................................................49

Figure 5.1. 12-Bit ADC0 Functional Block Diagram............................................................49
Figure 5.2. Typical Temperature Sensor Transfer Function..................................................50
Figure 5.3. ADC0 Track and Conversion Example Timing ..................................................52
Figure 5.4. ADC0 Equivalent Input Circuits .........................................................................53
Figure 5.5. AMX0CF: AMUX0 Configuration Register.......................................................54
Figure 5.6. AMX0SL: AMUX0 Channel Select Register .....................................................55
Figure 5.7. ADC0CF: ADC0 Configuration Register ...........................................................56
Figure 5.8. ADC0CN: ADC0 Control Register .....................................................................57
Figure 5.9. ADC0H: ADC0 Data Word MSB Register.........................................................58
Figure 5.10. ADC0L: ADC0 Data Word LSB Register ..........................................................58
Figure 5.11. ADC0 Data Word Example.................................................................................59
Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................60
Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register ................................60
Figure 5.14. ADC0LTH: ADC0 Less-Than Data High Byte Register ....................................61
Figure 5.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register .....................................61
Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data .62
Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....63
Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....64
Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......65

6. ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY) ..................................................................67

Page 10

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.1. 10-Bit ADC0 Functional Block Diagram............................................................67
Figure 6.2. Typical Temperature Sensor Transfer Function..................................................68
Figure 6.3. ADC0 Track and Conversion Example Timing ..................................................70
Figure 6.4. ADC0 Equivalent Input Circuits .........................................................................71
Figure 6.5. AMX0CF: AMUX0 Configuration Register.......................................................72
Figure 6.6. AMX0SL: AMUX0 Channel Select Register .....................................................73
Figure 6.7. ADC0CF: ADC0 Configuration Register ...........................................................74
Figure 6.8. ADC0CN: ADC0 Control Register .....................................................................75
Figure 6.9. ADC0H: ADC0 Data Word MSB Register.........................................................76
Figure 6.10. ADC0L: ADC0 Data Word LSB Register ..........................................................76
Figure 6.11. ADC0 Data Word Example.................................................................................77
Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register...............................78
Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register ................................78
Figure 6.14. ADC0LTH: ADC0 Less-Than Data High Byte Register ....................................79
Figure 6.15. ADC0LTL: ADC0 Less-Than Data Low Byte Register .....................................79
Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data .80
Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....81
Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....82
Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......83

7. ADC2 (8-BIT ADC) ...............................................................................................................85

Figure 7.1. ADC2 Functional Block Diagram .......................................................................85
Figure 7.2. ADC2 Track and Conversion Example Timing ..................................................87
Figure 7.3. ADC2 Equivalent Input Circuit...........................................................................88
Figure 7.4. AMX2CF: AMUX2 Configuration Register.......................................................89
Figure 7.5. AMX2SL: AMUX2 Channel Select Register .....................................................90
Figure 7.6. ADC2CF: ADC2 Configuration Register ...........................................................91
Figure 7.7. ADC2CN: ADC2 Control Register .....................................................................92
Figure 7.8. ADC2: ADC2 Data Word Register .....................................................................93
Figure 7.9. ADC2 Data Word Example.................................................................................93
Figure 7.10. ADC2 Window Compare Examples, Single-Ended Mode .................................94
Figure 7.11. ADC2 Window Compare Examples, Differential Mode ....................................95
Figure 7.12. ADC2GT: ADC2 Greater-Than Data Byte Register...........................................96
Figure 7.13. ADC2LT: ADC2 Less-Than Data Byte Register................................................96

8. DACS, 12-BIT VOLTAGE MODE ......................................................................................99

Figure 8.1. DAC Functional Block Diagram .........................................................................99
Figure 8.2. DAC0H: DAC0 High Byte Register .................................................................101
Figure 8.3. DAC0L: DAC0 Low Byte Register ..................................................................101
Figure 8.4. DAC0CN: DAC0 Control Register ...................................................................102
Figure 8.5. DAC1H: DAC1 High Byte Register .................................................................103
Figure 8.6. DAC1L: DAC1 Low Byte Register ..................................................................103
Figure 8.7. DAC1CN: DAC1 Control Register ...................................................................104

9. VOLTAGE REFERENCE (C8051F120/2/4/6) .................................................................107

Figure 9.1. Voltage Reference Functional Block Diagram..................................................107
Figure 9.2. REF0CN: Reference Control Register ..............................................................108

10. VOLTAGE REFERENCE (C8051F121/3/5/7) .................................................................109

DS008-1.1-JUN03

Page 11

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 10.1. Voltage Reference Functional Block Diagram .................................................109
Figure 10.2. REF0CN: Reference Control Register ..............................................................110

11. COMPARATORS................................................................................................................111

Figure 11.1. Comparator Functional Block Diagram ............................................................111
Figure 11.2. Comparator Hysteresis Plot...............................................................................113
Figure 11.3. CPT0CN: Comparator0 Control Register .........................................................114
Figure 11.4. CPT0MD: Comparator0 Mode Selection Register ...........................................115
Figure 11.5. CPT1CN: Comparator1 Control Register .........................................................116
Figure 11.6. CPT1MD: Comparator1 Mode Selection Register ...........................................117

12. CIP-51 MICROCONTROLLER........................................................................................119

Figure 12.1. CIP-51 Block Diagram .....................................................................................119
Figure 12.2. Memory Map .....................................................................................................125
Figure 12.3. PSBANK: Program Space Bank Select Register ..............................................126
Figure 12.4. Address Memory Map for Instruction Fetches..................................................126
Figure 12.5. SFR Page Stack .................................................................................................129
Figure 12.6. SFR Page Stack While Using SFR Page 0x0F To Access Port 5 .....................130
Figure 12.7. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs ..............131
Figure 12.8. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR...........132
Figure 12.9. SFR Page Stack Upon Return From PCA Interrupt ..........................................133
Figure 12.10. SFR Page Stack Upon Return From ADC2 Window Interrupt.......................134
Figure 12.11. SFRPGCN: SFR Page Control Register..........................................................135
Figure 12.12. SFRPAGE: SFR Page Register .......................................................................135
Figure 12.13. SFRNEXT: SFR Next Register .......................................................................136
Figure 12.14. SFRLAST: SFR Last Register ........................................................................136
Figure 12.15. SP: Stack Pointer .............................................................................................143
Figure 12.16. DPL: Data Pointer Low Byte ..........................................................................143
Figure 12.17. DPH: Data Pointer High Byte .........................................................................143
Figure 12.18. PSW: Program Status Word ............................................................................144
Figure 12.19. ACC: Accumulator..........................................................................................145
Figure 12.20. B: B Register ...................................................................................................145
Figure 12.21. IE: Interrupt Enable .........................................................................................149
Figure 12.22. IP: Interrupt Priority ........................................................................................150
Figure 12.23. EIE1: Extended Interrupt Enable 1 .................................................................151
Figure 12.24. EIE2: Extended Interrupt Enable 2 .................................................................152
Figure 12.25. EIP1: Extended Interrupt Priority 1.................................................................153
Figure 12.26. EIP2: Extended Interrupt Priority 2.................................................................154
Figure 12.27. PCON: Power Control.....................................................................................156

13. MULTIPLY AND ACCUMULATE (MAC0) ...................................................................157

Figure 13.1. MAC0 Block Diagram ......................................................................................157
Figure 13.2. Integer Mode Data Representation....................................................................158
Figure 13.3. Fractional Mode Data Representation ...............................................................158
Figure 13.4. MAC0 Pipeline..................................................................................................159
Figure 13.5. Multiply and Accumulate Example...................................................................160
Figure 13.6. Multiply Only Example.....................................................................................161
Figure 13.7. MAC0 Accumulator Shift Example ..................................................................161

Page 12

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 13.8. MAC0CF: MAC0 Configuration Register ........................................................162
Figure 13.9. MAC0STA: MAC0 Status Register ..................................................................163
Figure 13.10. MAC0AH: MAC0 A High Byte Register .......................................................163
Figure 13.11. MAC0AL: MAC0 A Low Byte Register ........................................................164
Figure 13.12. MAC0BH: MAC0 B High Byte Register........................................................164
Figure 13.13. MAC0BL: MAC0 B Low Byte Register.........................................................164
Figure 13.14. MAC0ACC3: MAC0 Accumulator Byte 3 Register.......................................164
Figure 13.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register.......................................165
Figure 13.16. MAC0ACC1: MAC0 Accumulator Byte 1 Register.......................................165
Figure 13.17. MAC0ACC0: MAC0 Accumulator Byte 0 Register.......................................165
Figure 13.18. MAC0OVR: MAC0 Accumulator Overflow Register....................................165
Figure 13.19. MAC0RNDH: MAC0 Rounding Register High Byte.....................................166
Figure 13.20. MAC0RNDL: MAC0 Rounding Register Low Byte......................................166

14. RESET SOURCES ..............................................................................................................167

Figure 14.1. Reset Sources ....................................................................................................167
Figure 14.2. Reset Timing .....................................................................................................168
Figure 14.3. WDTCN: Watchdog Timer Control Register ...................................................170
Figure 14.4. RSTSRC: Reset Source Register.......................................................................171

15. OSCILLATORS...................................................................................................................173

Figure 15.1. Oscillator Diagram ............................................................................................173
Figure 15.2. OSCICL: Internal Oscillator Calibration Register ............................................174
Figure 15.3. OSCICN: Internal Oscillator Control Register .................................................174
Figure 15.4. CLKSEL: System Clock Selection Register .....................................................175
Figure 15.5. OSCXCN: External Oscillator Control Register...............................................176
Figure 15.6. PLL Block Diagram ..........................................................................................178
Figure 15.7. PLL0CN: PLL Control Register........................................................................180
Figure 15.8. PLL0DIV: PLL Pre-divider Register ................................................................180
Figure 15.9. PLL0MUL: PLL Clock Scaler Register ............................................................181
Figure 15.10. PLL0FLT: PLL Filter Register........................................................................181

16. FLASH MEMORY ..............................................................................................................185

Figure 16.1. FLASH Memory Map for MOVC Read and MOVX Write Operations...........186
Figure 16.2. FLASH Program Memory Map and Security Bytes .........................................189
Figure 16.3. FLACL: FLASH Access Limit .........................................................................190
Figure 16.4. FLSCL: FLASH Memory Control ....................................................................191
Figure 16.5. PSCTL: Program Store Read/Write Control .....................................................192

17. BRANCH TARGET CACHE.............................................................................................193

Figure 17.1. Branch Target Cache Data Flow .......................................................................193
Figure 17.2. Branch Target Cache Organiztion .....................................................................194
Figure 17.3. Cache Lock Operation.......................................................................................195
Figure 17.4. CCH0CN: Cache Control Register....................................................................196
Figure 17.5. CCH0TN: Cache Tuning Register ....................................................................197
Figure 17.6. CCH0LC: Cache Lock Control Register...........................................................197
Figure 17.7. CCH0MA: Cache Miss Accumulator................................................................198
Figure 17.8. FLSTAT: FLASH Status...................................................................................198

18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................199

DS008-1.1-JUN03

Page 13

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 18.1. EMI0CN: External Memory Interface Control .................................................201
Figure 18.2. EMI0CF: External Memory Configuration .......................................................201
Figure 18.3. Multiplexed Configuration Example.................................................................202
Figure 18.4. Non-multiplexed Configuration Example .........................................................203
Figure 18.5. EMIF Operating Modes.....................................................................................204
Figure 18.6. EMI0TC: External Memory Timing Control ....................................................206
Figure 18.7. Non-multiplexed 16-bit MOVX Timing ...........................................................207
Figure 18.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................208
Figure 18.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................209
Figure 18.10. Multiplexed 16-bit MOVX Timing .................................................................210
Figure 18.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................211
Figure 18.12. Multiplexed 8-bit MOVX with Bank Select Timing.......................................212

19. PORT INPUT/OUTPUT .....................................................................................................215

Figure 19.1. Port I/O Cell Block Diagram.............................................................................215
Figure 19.2. Port I/O Functional Block Diagram ..................................................................216
Figure 19.3. Priority Crossbar Decode Table ........................................................................217
Figure 19.4. Priority Crossbar Decode Table ........................................................................220
Figure 19.5. Priority Crossbar Decode Table ........................................................................221
Figure 19.6. Crossbar Example: ............................................................................................223
Figure 19.7. XBR0: Port I/O Crossbar Register 0 .................................................................224
Figure 19.8. XBR1: Port I/O Crossbar Register 1 .................................................................225
Figure 19.9. XBR2: Port I/O Crossbar Register 2 .................................................................226
Figure 19.10. P0: Port0 Data Register ...................................................................................227
Figure 19.11. P0MDOUT: Port0 Output Mode Register.......................................................227
Figure 19.12. P1: Port1 Data Register ...................................................................................228
Figure 19.13. P1MDIN: Port1 Input Mode Register .............................................................228
Figure 19.14. P1MDOUT: Port1 Output Mode Register.......................................................229
Figure 19.15. P2: Port2 Data Register ...................................................................................229
Figure 19.16. P2MDOUT: Port2 Output Mode Register.......................................................230
Figure 19.17. P3: Port3 Data Register ...................................................................................230
Figure 19.18. P3MDOUT: Port3 Output Mode Register.......................................................231
Figure 19.19. P4: Port4 Data Register ...................................................................................233
Figure 19.20. P4MDOUT: Port4 Output Mode Register.......................................................233
Figure 19.21. P5: Port5 Data Register ...................................................................................234
Figure 19.22. P5MDOUT: Port5 Output Mode Register.......................................................234
Figure 19.23. P6: Port6 Data Register ...................................................................................235
Figure 19.24. P6MDOUT: Port6 Output Mode Register.......................................................235
Figure 19.25. P7: Port7 Data Register ...................................................................................236
Figure 19.26. P7MDOUT: Port7 Output Mode Register.......................................................236

20. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................237

Figure 20.1. SMBus0 Block Diagram ...................................................................................237
Figure 20.2. Typical SMBus Configuration ..........................................................................238
Figure 20.3. SMBus Transaction ...........................................................................................239
Figure 20.4. Typical Master Transmitter Sequence...............................................................240
Figure 20.5. Typical Master Receiver Sequence ...................................................................240

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 20.6. Typical Slave Transmitter Sequence .................................................................241
Figure 20.7. Typical Slave Receiver Sequence .....................................................................241
Figure 20.8. SMB0CN: SMBus0 Control Register ...............................................................243
Figure 20.9. SMB0CR: SMBus0 Clock Rate Register ..........................................................244
Figure 20.10. SMB0DAT: SMBus0 Data Register ...............................................................245
Figure 20.11. SMB0ADR: SMBus0 Address Register..........................................................245
Figure 20.12. SMB0STA: SMBus0 Status Register..............................................................246

21. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................249

Figure 21.1. SPIBlock Diagram............................................................................................249
Figure 21.2. Multiple-Master Mode Connection Diagram ....................................................252
Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram ...252
Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram ....252
Figure 21.5. Master Mode Data/Clock Timing......................................................................254
Figure 21.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................................255
Figure 21.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................................255
Figure 21.8. SPI0CFG: SPI0 Configuration Register............................................................256
Figure 21.9. SPI0CN: SPI0 Control Register ........................................................................257
Figure 21.10. SPI0CKR: SPI0 Clock Rate Register ..............................................................258
Figure 21.11. SPI0DAT: SPI0 Data Register ........................................................................259
Figure 21.12. SPIMaster Timing (CKPHA = 0) ...................................................................260
Figure 21.13. SPIMaster Timing (CKPHA = 1) ...................................................................260
Figure 21.14. SPISlave Timing (CKPHA = 0) .....................................................................261
Figure 21.15. SPISlave Timing (CKPHA = 1) .....................................................................261

22. UART0 ..................................................................................................................................263

Figure 22.1. UART0 Block Diagram.....................................................................................263
Figure 22.2. UART0 Mode 0 Timing Diagram .....................................................................264
Figure 22.3. UART0 Mode 0 Interconnect............................................................................264
Figure 22.4. UART0 Mode 1 Timing Diagram .....................................................................265
Figure 22.5. UART0 Modes 2 and 3 Timing Diagram..........................................................266
Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram ............................................267
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram .......................................269
Figure 22.8. SCON0: UART0 Control Register....................................................................271
Figure 22.9. SSTA0: UART0 Status and Clock Selection Register ......................................272
Figure 22.10. SBUF0: UART0 Data Buffer Register............................................................273
Figure 22.11. SADDR0: UART0 Slave Address Register ....................................................273
Figure 22.12. SADEN0: UART0 Slave Address Enable Register ........................................273

23. UART1 ..................................................................................................................................275

Figure 23.1. UART1 Block Diagram.....................................................................................275
Figure 23.2. UART1 Baud Rate Logic ..................................................................................276
Figure 23.3. UART Interconnect Diagram ............................................................................277
Figure 23.4. 8-Bit UART Timing Diagram ...........................................................................277
Figure 23.5. 9-Bit UART Timing Diagram ...........................................................................278
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram .......................................279
Figure 23.7. SCON1: Serial Port 1 Control Register.............................................................280
Figure 23.8. SBUF1: Serial (UART1) Port Data Buffer Register .........................................281

DS008-1.1-JUN03

Page 15

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

24. TIMERS................................................................................................................................285

Figure 24.1. T0 Mode 0 Block Diagram................................................................................286
Figure 24.2. T0 Mode 2 Block Diagram................................................................................287
Figure 24.3. T0 Mode 3 Block Diagram................................................................................288
Figure 24.4. TCON: Timer Control Register.........................................................................289
Figure 24.5. TMOD: Timer Mode Register...........................................................................290
Figure 24.6. CKCON: Clock Control Register......................................................................291
Figure 24.7. TL0: Timer 0 Low Byte ....................................................................................292
Figure 24.8. TL1: Timer 1 Low Byte ....................................................................................292
Figure 24.9. TH0: Timer 0 High Byte ...................................................................................292
Figure 24.10. TH1: Timer 1 High Byte .................................................................................292
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram ....................................................294
Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram..............................................295
Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers ..............................................297
Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers ....................................298
Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte................................299
Figure 24.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte ..............................299
Figure 24.17. TMRnL: Timer 2, 3, and 4 Low Byte .............................................................299
Figure 24.18. TMRnH Timer 2, 3, and 4 High Byte .............................................................300

25. PROGRAMMABLE COUNTER ARRAY .......................................................................301

Figure 25.1. PCA Block Diagram..........................................................................................301
Figure 25.2. PCA Counter/Timer Block Diagram .................................................................302
Figure 25.3. PCA Interrupt Block Diagram...........................................................................303
Figure 25.4. PCA Capture Mode Diagram ............................................................................304
Figure 25.5. PCA Software Timer Mode Diagram................................................................305
Figure 25.6. PCA High Speed Output Mode Diagram ..........................................................306
Figure 25.7. PCA Frequency Output Mode ...........................................................................307
Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................................308
Figure 25.9. PCA 16-Bit PWM Mode ...................................................................................309
Figure 25.10. PCA0CN: PCA Control Register ....................................................................310
Figure 25.11. PCA0MD: PCA0 Mode Register ....................................................................311
Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers .................................312
Figure 25.13. PCA0L: PCA0 Counter/Timer Low Byte .......................................................313
Figure 25.14. PCA0H: PCA0 Counter/Timer High Byte ......................................................313
Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte ..............................................314
Figure 25.16. PCA0CPHn: PCA0 Capture Module High Byte .............................................314

26. JTAG (IEEE 1149.1)............................................................................................................315

Figure 26.1. IR: JTAG Instruction Register ..........................................................................315
Figure 26.2. DEVICEID: JTAG Device ID Register ............................................................317
Figure 26.3. FLASHCON: JTAG Flash Control Register.....................................................319
Figure 26.4. FLASHDAT: JTAG Flash Data Register..........................................................320
Figure 26.5. FLASHADR: JTAG Flash Address Register ....................................................320

DS008-1.1-JUN03

Page 17

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

LIST OF TABLES

1. SYSTEM OVERVIEW ........................................................................................................19

Table 1.1. Product Selection Guide .......................................................................................20

2. ABSOLUTE MAXIMUM RATINGS .................................................................................36

Table 2.1. Absolute Maximum Ratings* ...............................................................................36

3. GLOBAL DC ELECTRICAL CHARACTERISTICS .....................................................37

Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3) ....................................37
Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) ....................................38

4. PINOUT AND PACKAGE DEFINITIONS .......................................................................39

Table 4.1. Pin Definitions ......................................................................................................39

5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) .................................................................49

Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/5) ................................66

6. ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY) .................................................................67

Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F122/3/6/7) ................................84

7. ADC2 (8-BIT ADC) ..............................................................................................................85

Table 7.1. ADC2 Electrical Characteristics ...........................................................................97

8. DACS, 12-BIT VOLTAGE MODE .....................................................................................99

Table 8.1. DAC Electrical Characteristics ...........................................................................105

9. VOLTAGE REFERENCE (C8051F120/2/4/6) ................................................................107

Table 9.1. Voltage Reference Electrical Characteristics .....................................................108

10. VOLTAGE REFERENCE (C8051F121/3/5/7) ................................................................109

Table 10.1.Voltage Reference Electrical Characteristics .....................................................110

11. COMPARATORS ...............................................................................................................111

Table 11.1.Comparator Electrical Characteristics ................................................................118

12. CIP-51 MICROCONTROLLER .......................................................................................119

Table 12.1.CIP-51 Instruction Set Summary ........................................................................121
Table 12.2.Special Function Register (SFR) Memory Map .................................................137
Table 12.3.Special Function Registers .................................................................................138
Table 12.4.Interrupt Summary ..............................................................................................147

13. MULTIPLY AND ACCUMULATE (MAC0) ..................................................................157

Table 13.1.MAC0 Rounding (MAC0SAT = 0) ....................................................................160

14. RESET SOURCES .............................................................................................................167

Table 14.1.Reset Electrical Characteristics ..........................................................................172

15. OSCILLATORS ..................................................................................................................173

Table 15.1.Oscillator Electrical Characteristics ...................................................................173
Table 15.2.PLL Frequency Characteristics ...........................................................................182
Table 15.3.PLL Lock Timing Characteristics ......................................................................182

16. FLASH MEMORY .............................................................................................................185

Table 16.1.FLASH Electrical Characteristics .......................................................................188

17. BRANCH TARGET CACHE ............................................................................................193
18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM ......................199

Table 18.1.AC Parameters for External Memory Interface ................................................213

19. PORT INPUT/OUTPUT ....................................................................................................215

Page 18

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 19.1.Port I/O DC Electrical Characteristics ................................................................215

20. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) ................................................237

Table 20.1.SMB0STA Status Codes and States ...................................................................247

21. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) ........................................249

Table 21.1.SPISlave Timing Parameters .............................................................................262

22. UART0 .................................................................................................................................263

Table 22.1.UART0 Modes ....................................................................................................264
Table 22.2.Oscillator Frequencies for Standard Baud Rates ................................................270

23. UART1 .................................................................................................................................275

Table 23.1.Timer Settings for Standard Baud Rates Using The Internal Oscillator ............282
Table 23.2.Timer Settings for Standard Baud Rates Using an External Oscillator ..............282
Table 23.3.Timer Settings for Standard Baud Rates Using an External Oscillator ..............283
Table 23.4.Timer Settings for Standard Baud Rates Using the PLL ....................................283
Table 23.5.Timer Settings for Standard Baud Rates Using the PLL ....................................284

24. TIMERS ...............................................................................................................................285
25. PROGRAMMABLE COUNTER ARRAY ......................................................................301

Table 25.1.PCA Timebase Input Options .............................................................................302
Table 25.2.PCA0CPM Register Settings for PCA Capture/Compare Modules ...................303

26. JTAG (IEEE 1149.1) ...........................................................................................................315

Table 26.1.Boundary Data Register Bit Definitions .............................................................316

DS008-1.1-JUN03

Page 19

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

SYSTEM OVERVIEW

The C8051F12x devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins
(C8051F120/2/4/6) or 32 digital I/O pins (C8051F121/3/5/7). Highlighted features are listed below; refer to Table 1.1
for specific product feature selection.

High-Speed pipelined 8051-compatible CIP-51 microcontroller core (up to 100 MIPS for C8051F120/1/2/3 and
50 MIPS for C8051F124/5/6/7)

In-system, full-speed, non-intrusive debug interface (on-chip)

True 12-bit (C8051F120/1/4/5) or 10-bit (C8051F122/3/6/7) 100 ksps ADC with PGA and 8-channel analog
multiplexer

True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer

Two 12-bit DACs with programmable update scheduling

2-cycle 16 by 16 Multiply and Accumulate Engine (C8051F120/1/2/3)

128k bytes of in-system programmable FLASH memory

8448 (8k + 256) bytes of on-chip RAM

External Data Memory Interface with 64k byte address space

SPI, SMBus/I

C, and (2) UART serial interfaces implemented in hardware

Five general purpose 16-bit Timers

Programmable Counter/Timer Array with 6 capture/compare modules

On-chip Watchdog Timer, VDD Monitor, and Temperature Sensor

With on-chip VDD monitor, Watchdog Timer, and clock oscillator, the C8051F12x devices are truly stand-alone Sys-
tem-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user firmware.
The FLASH memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing
field upgrades of the 8051 firmware.

On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging
using the production MCU installed in the final application. This debug system supports inspection and modification
of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and
digital peripherals are fully functional while debugging using JTAG.

Each MCU is specified for operation over the industrial temperature range (-45° C to +85° C). The Port I/Os, /RST,
and JTAG pins are tolerant for input signals up to 5 V. The C8051F120/2/4/6 are available in a 100-pin TQFP pack-
age (see block diagrams in Figure 1.1 and Figure 1.3). The C8051F121/3/5/7 are available in a 64-pin TQFP package
(see block diagrams in Figure 1.2 and Figure 1.4).

Page 20

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 1.1. Product Selection Guide

MIPS

(Peak)

e
m

r
y

-
c
y

c
l
e

ternal

Memo

Interf

ace

s
/
I

UAR

i
mers

6-b

i
t
)

r
o

ramm

abl

t
e
r

rray

i
g

i
t
a
lP

r
tI/

'
s

-b

i
t

00k

put

-b

i
t

00k

put

-
bi

00k

Inp

l
t
ag

erence

e
mperatu

r
e

ens

DAC

Res

tio

(
b

its)

DAC

t
s

Analo

mpar

ators

ack

age

C8051F120

100

128k 8448

! ! ! !

! !

100TQFP

C8051F121

100

128k 8448

! ! ! !

! !

64TQFP

C8051F122

100

128k 8448

! ! ! !

! !

100TQFP

C8051F123

100

128k 8448

! ! ! !

! !

64TQFP

C8051F124

128k 8448

! ! !

! !

100TQFP

C8051F125

128k 8448

! ! !

! !

64TQFP

C8051F126

128k 8448

! ! !

! !

100TQFP

C8051F127

128k 8448

! ! !

! !

64TQFP

DS008-1.1-JUN03

Page 21

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 1.1. C8051F120/124 Block Diagram

P0, P1,

P2, P3

Latches

JTAG

Logic

TCK

TMS

TDI

TDO

UART1

SMBus

SPI Bus

PCA

128kbyte

FLASH

256 byte

RAM

VDD

Monitor

SFR Bus

8
0
5
1

Timers 0,

1, 2, 4

Timer 3/

RTC

P0
Drv

C
R
O
S
S
B
A
R

PortI/O

Config.

Crossbar

Config.

AV+

VDD

DGND

AGND

Reset

/RST

XTAL1

XTAL2

External Oscillator

Circuit

System

Clock

Calibrated Internal

Oscillator

Digital Power

Analog Power

Debug HW

Boundary Scan

8kbyte
XRAM

P2.0

P2.7

P1.0/AIN2.0

P1.7/AIN2.7

P0.0

P0.7

P1
Drv

P2
Drv

Data Bus

Address Bus

Bus Control

DAC1

DAC1

(12-Bit)

VREF

DAC0

(12-Bit)

ADC

100ksps

(12-Bit)

U
X

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

DAC0

CP0+

CP0-

CP1+

CP1-

VREF

TEMP

SENSOR

UART0

P3.0

P3.7

P3
Drv

8:1

MONEN

WDT

VREFD

VREF0

Prog
Gain

CP0

CP1

T
L

P4 Latch

P7 Latch

d
d

P5 Latch

P6 Latch

P7.0/D0

P7.7/D7

DRV

P5.0/A8

P5.7/A15

DRV

P6.0/A0

P6.7/A7

DRV

P4.5/ALE

P4.6/RD

P4.7/WR

P4.0

P4.4

Prog
Gain

ADC
500ksps
(8-Bit)

U
X

VREF2

PLL

Circuitry

External Data

Memory Bus

64x4 byte

cache

Page 22

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 1.2. C8051F121/125 Block Diagram

P0, P1,

P2, P3

Latches

JTAG

Logic

TCK

TMS

TDI

TDO

UART1

SMBus

SPI Bus

PCA

VDD

Monitor

Timers 0,

1, 2, 4

Timer 3/

RTC

P0
Drv

C
R
O
S
S
B
A
R

PortI/O

Config.

Crossbar

Config.

AV+

VDD

DGND

AGND

Reset

/RST

Digital Power

Analog Power

Debug HW

Boundary Scan

P2.0

P2.7

P1.0/AIN2.0

P1.7/AIN2.7

P0.0

P0.7

P1
Drv

P2
Drv

Data Bus

Address Bus

Bus Control

DAC1

DAC1

(12-Bit)

VREF

DAC0

(12-Bit)

ADC

100ksps

(12-Bit)

M
U

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

DAC0

CP0+

CP0-

CP1+

CP1-

VREF

TEMP

SENSOR

UART0

P3.0

P3.7

P3
Drv

8:1

MONEN

WDT

VREFA

Prog
Gain

CP0

CP1

T
L

P4 Latch

P7 Latch

d
d

P5 Latch

P6 Latch

DRV

Prog
Gain

ADC
500ksps
(8-Bit)

U
X

VREFA

AV+

XTAL1
XTAL2

External Oscillator

Circuit

System

Clock

Calibrated Internal

Oscillator

PLL

Circuitry

128kbyte

FLASH

256 byte

RAM

SFR Bus

8
0
5
1

8kbyte
XRAM

External Data

Memory Bus

64x4 byte

cache

DS008-1.1-JUN03

Page 23

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

P0, P1,

P2, P3

Latches

JTAG

Logic

TCK

TMS

TDI

TDO

UART1

SMBus

SPI Bus

PCA

VDD

Monitor

Timers 0,

1, 2, 4

Timer 3/

RTC

P0
Drv

C
R
O
S
S
B
A
R

PortI/O

Config.

Crossbar

Config.

AV+

VDD

DGND

AGND

Reset

/RST

Digital Power

Analog Power

Debug HW

Boundary Scan

P2.0

P2.7

P1.0/AIN2.0

P1.7/AIN2.7

P0.0

P0.7

P1
Drv

P2
Drv

Data Bus

Address Bus

Bus Control

DAC1

DAC1

(12-Bit)

VREF

DAC0

(12-Bit)

ADC

100ksps

(10-Bit)

U
X

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

DAC0

CP0+

CP0-

CP1+

CP1-

VREF

TEMP

SENSOR

UART0

P3.0

P3.7

P3
Drv

8:1

MONEN

WDT

VREFD

VREF0

Prog
Gain

CP0

CP1

T
L

P4 Latch

P7 Latch

d
d

P5 Latch

P6 Latch

P7.0/D0

P7.7/D7

DRV

P5.0/A8

P5.7/A15

DRV

P6.0/A0

P6.7/A7

DRV

P4.5/ALE

P4.6/RD

P4.7/WR

P4.0

P4.4

Prog
Gain

ADC
500ksps
(8-Bit)

U
X

VREF2

XTAL1

XTAL2

External Oscillator

Circuit

System

Clock

Calibrated Internal

Oscillator

PLL

Circuitry

128kbyte

FLASH

256 byte

RAM

SFR Bus

8
0
5
1

8kbyte
XRAM

External Data

Memory Bus

64x4 byte

cache

Figure 1.3. C8051F122/126 Block Diagram

Page 24

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

P0, P1,

P2, P3

Latches

JTAG

Logic

TCK

TMS

TDI

TDO

UART1

SMBus

SPI Bus

PCA

VDD

Monitor

Timers 0,

1, 2, 4

Timer 3/

RTC

P0
Drv

C
R
O
S
S
B
A
R

PortI/O

Config.

Crossbar

Config.

AV+

VDD

DGND

AGND

Reset

/RST

Digital Power

Analog Power

Debug HW

Boundary Scan

P2.0

P2.7

P1.0/AIN2.0

P1.7/AIN2.7

P0.0

P0.7

P1
Drv

P2
Drv

Data Bus

Address Bus

Bus Control

DAC1

DAC1

(12-Bit)

VREF

DAC0

(12-Bit)

ADC

100ksps

(10-Bit)

M
U

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

DAC0

CP0+

CP0-

CP1+

CP1-

VREF

TEMP

SENSOR

UART0

P3.0

P3.7

P3
Drv

8:1

MONEN

WDT

VREFA

Prog
Gain

CP0

CP1

T
L

P4 Latch

P7 Latch

d
d

P5 Latch

P6 Latch

DRV

Prog
Gain

ADC
500ksps
(8-Bit)

U
X

VREFA

AV+

XTAL1
XTAL2

External Oscillator

Circuit

System

Clock

Calibrated Internal

Oscillator

PLL

Circuitry

128kbyte

FLASH

256 byte

RAM

SFR Bus

8
0
5
1

8kbyte
XRAM

External Data

Memory Bus

64x4 byte

cache

Figure 1.4. C8051F123/127 Block Diagram

DS008-1.1-JUN03

Page 25

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.1.

CIP-51TM Microcontroller Core

1.1.1.

Fully 8051 Compatible

The C8051F12x family utilizes Cygnal's proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible
with the MCS-51TM instruction set; standard 803x/805x assemblers and compilers can be used to develop software.
The core has all the peripherals included with a standard 8052, including five 16-bit counter/timers, two full-duplex
UARTs, 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space, and 8/4 byte-wide I/O
Ports.

1.1.2.

Improved Throughput

The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute with a maximum system clock of 12-to-24 MHz. By contrast, the CIP-51 core executes 70% of its instructions in
one or two system clock cycles, with only four instructions taking more than four system clock cycles.

The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each
execution time.

With the CIP-51's maximum system clock at 100 MHz, the C8051F120/1/2/3 have a peak throughput of 100 MIPS
(the C8051F124/5/6/7 have a peak throughput of 50 MIPS).

Clocks to Execute

2/3

3/4

4/5

Number of I nstructions

Page 26

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.1.3.

Additional Features

The C8051F12x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve over-
all performance and ease of use in end applications.

The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051),
allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires
less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when
building multi-tasking, real-time systems.

There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock
detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input pin, and the /RST
pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be
output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the
user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be perma-
nently enabled in software after a power-on reset during MCU initialization.

The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If
desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic reso-
nator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switch-
ing to the 24.5 MHz internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system
clock speeds for increased throughput.

WDT

XTAL1

XTAL2

OSC

Internal

Clock

Generator

System
Clock

CIP-51

Microcontroller

Core

Missing

Clock

Detector

(one-

shot)

obe

Software Reset

Extended Interrupt

Handler

Clock Select

/RST

+
-

VDD

Supply

Reset

Timeout

(wired-OR)

System Reset

Supply
Monitor

PRE

Reset
Funnel

+
-

CP0+

Comparator0

CP0-

(Port

I/O)

Crossbar

CNVSTR

(CNVSTR

reset

enable)

(CP0
reset

enable)

nabl

PLL

Circuitry

Figure 1.5. On-Board Clock and Reset

DS008-1.1-JUN03

Page 27

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.2.

On-Chip Memory

The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the
upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct
addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indi-
rect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes
can be byte addressable or bit addressable.

The CIP-51 in the C8051F12x MCUs additionally has an on-chip 8k byte RAM block and an external memory inter-
face (EMIF) for accessing off-chip data memory. The on-chip 8k byte block can be addressed over the entire 64k
external data memory address range (overlapping 8k boundaries). External data memory address space can be
mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 8k directed to
on-chip, above 8k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data
lines.

The MCU's program memory consists of 128k bytes of banked FLASH memory. This memory may be repro-
grammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. The 1024 bytes from
addresses 0x1FC00 to 0x1FFFF are reserved. There are also two 128 byte sectors at addresses 0x20000 to 0x200FF,
which may be used by software. See Figure 1.6 for the MCU system memory map.

PROGRAM/DATA MEMORY

(FLASH)

(Directand Indirect

Addressing)

0x00

0x7F

Upper 128 RAM

(IndirectAddressing

Only)

0x80

0xFF

DATA MEMORY (RAM)

General Purpose

Registers

0x1F

0x20

0x2F

BitAddressable

0x30

INTERNAL DATA ADDRESS SPACE

EXTERNAL DATA ADDRESS SPACE

XRAM - 8192 Bytes

(accessable using MOVX

instruction)

0x0000

0x1FFF

Off-chip XRAM space

0x2000

0xFFFF

FLASH

(In-System

Programmable in 1024

Byte Sectors)

0x00000

0x1FFFF

RESERVED

0x1FC00

0x1FBFF

Scrachpad Memory

(DATA only)

0x200FF

0x20000

Special Function

Registers

(DirectAddressing Only)

Lower 128 RAM
(Directand Indirect
Addressing)

Up To

256 SFR Pages

Figure 1.6. On-Chip Memory Map

Page 28

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.3.

JTAG Debug and Boundary Scan

The C8051F12x device family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full
speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG inter-
face. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing pur-
poses.

Cygnal's debugging system supports inspection and modification of memory and registers, breakpoints, watchpoints,
a stack monitor, and single stepping. No additional target RAM, program memory, timers, or communications chan-
nels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the
peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a
breakpoint in order to keep them synchronized.

The C8051F120DK development kit provides all the hardware and software necessary to develop application code
and perform in-circuit debugging with the C8051F12x MCUs. The kit includes software with a developer's studio and
debugger, an integrated 8051 assembler, and an RS-232 to JTAG serial adapter. It also has a target application board
with the associated MCU installed, plus the RS-232 and JTAG cables, and wall-mount power supply. The Develop-
ment Kit requires a Windows 95/98/NT/ME computer with one available RS-232 serial port. As shown in Figure 1.7,
the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial Adapter to the
user's application board, picking up the four JTAG pins and VDD and GND. The Serial Adapter takes its power from
the application board. For applications where there is not sufficient power available from the target system, the pro-
vided power supply can be connected directly to the Serial Adapter.

Cygnal's debug environment is a vastly superior configuration for developing and debugging embedded applications
compared to standard MCU emulators, which use on-board "ICE Chips" and target cables and require the MCU in the
application board to be socketed. Cygnal's debug environment both increases ease of use and preserves the perfor-
mance of the precision analog peripherals.

TARGET PCB

RS-232

Serial

Adapter

C8051

F12x

VDD

GND

JTAG (x4), VDD, GND

WINDOWS 95/98/NT/ME/2000

CYGNAL Integrated

DevelopmentEnvironment

Figure 1.7. Development/In-System Debug Diagram

DS008-1.1-JUN03

Page 29

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.4.

16 x 16 MAC (Multiply and Accumulate) Engine

The C8051F120/1/2/3 devices include a multiply and accumulate engine which can be used to speed up many mathe-
matical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or frac-
tional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles. A rounding
engine provides a rounded 16-bit fractional result after an additional (third) SYSCLK cycle. MAC0 also contains a 1-
bit arithmetic shifter that will left or right-shift the contents of the 40-bit accumulator in a single SYSCLK cycle.

MAC0CF

MAC0MS

MAC0FM

MAC0SAT

MAC0CA

MAC0SD

MAC0SC

MAC0STA

MAC0N

MAC0SO

MAC0Z

MAC0HO

16 x 16 Multiply

MAC0RNDH

MAC0RNDL

MAC0 Rounding Register

MAC0OVR

MAC0ACC3

MAC0ACC2

MAC0ACC1

MAC0ACC0

MAC0 Accumulator

40 bitAdd

MAC0MS

Rounding Engine

1 bitShift

MAC0FM

Flag Logic

MAC0BH

MAC0BL

MAC0 B Register

MAC0AH

MAC0AL

MAC0 A Register

Figure 1.8. MAC0 Block Diagram

Page 30

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.5.

Programmable Digital I/O and Crossbar

The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F120/2/4/6 have 4 additional ports (4,
5, 6, and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhance-
ments.

Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power
applications.

Perhaps the most unique enhancement is the Digital Crossbar. This is a large digital switching network that allows
mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See Figure 1.9) Unlike micro-
controllers with standard multiplexed digital I/O, all combinations of functions are supported.

The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion inputs, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Con-
trol registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for
the particular application.

External

Pins

Digital

Crossbar

Priority

Decoder

SMBus

SPI

UART0

PCA

T0, T1,

T2, T2EX,

T4,T4EX

/INT0,

/INT1

P1.0

P1.7

P2.0

P2.7

P0.0

P0.7

Highest

Priority

Lowest
Priority

Comptr.
Outputs

(
I
n

ter

nal

tal

i
gna

)

Highest

Priority

Lowest
Priority

UART1

/SYSCLK divided by 1,2,4, or 8

CNVSTR0/2

P3.0

P3.7

P0MDOUT, P1MDOUT,

P2MDOUT, P3MDOUT

Registers

XBR0, XBR1,

XBR2, P1MDIN

Registers

I/O

Cells

I/O

Cells

I/O

Cells

I/O

Cells

Port

Latches

(P2.0-P2.7)

(P1.0-P1.7)

(P0.0-P0.7)

(P3.0-P3.7)

ADC2

Input

To External

Memory

Interface

(EMIF)

Figure 1.9. Digital Crossbar Diagram

DS008-1.1-JUN03

Page 31

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.6.

Programmable Counter Array

The C8051F12x MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five
16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 6 pro-
grammable capture/compare modules. The timebase is clocked from one of six sources: the system clock divided by
12, the system clock divided by 4, Timer 0 overflow, an External Clock Input (ECI pin), the system clock, or the
external oscillator source divided by 8.

Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture, Software
Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. The
PCA Capture/Compare Module I/O and External Clock Input are routed to the MCU Port I/O via the Digital Cross-
bar.

Capture/Compare

Module 1

Capture/Compare

Module 0

Capture/Compare

Module 2

Capture/Compare

Module 3

CE
X

Crossbar

CE
X

PortI/O

16-BitCounter/Timer

PCA

CLOCK

MUX

SYSCLK/12

SYSCLK/4

Timer 0 Overflow

ECI

SYSCLK

External Clock/8

Capture/Compare

Module 4

CE
X

Capture/Compare

Module 5

CE
X

Figure 1.10. PCA Block Diagram

DS008-1.1-JUN03

Page 33

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.8.

12-Bit Analog to Digital Converter

The C8051F120/1/4/5 have an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer and programma-
ble gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit linearity with an INL of
±1LSB. C8051F122/3/6/7 devices include a 10-bit SAR ADC with similar specifications and configuration options.
The ADC0 voltage reference is selected between the DAC0 output and an external VREF pin. On C8051F120/2/4/6
devices, ADC0 has its own dedicated VREF0 input pin; on C8051F121/3/5/7 devices, the ADC0 shares the VREFA
input pin with the 8-bit ADC2. The on-chip 15 ppm/°C voltage reference may generate the voltage reference for other
system components or the on-chip ADCs via the VREF output pin.

The ADC is under full control of the CIP-51 microcontroller via its associated Special Function Registers. One input
channel is tied to an internal temperature sensor, while the other eight channels are available externally. Each pair of
the eight external input channels can be configured as either two single-ended inputs or a single differential input.
The system controller can also put the ADC into shutdown mode to save power.

A programmable gain amplifier follows the analog multiplexer. The gain can be set in software from 0.5 to 16 in
powers of 2. The gain stage can be especially useful when different ADC input channels have widely varied input
voltage signals, or when it is necessary to "zoom in" on a signal with a large DC offset (in differential mode, a DAC
could be used to provide the DC offset).

Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of Timer 3, or an
external signal input. This flexibility allows the start of conversion to be triggered by software events, external HW
signals, or a periodic timer overflow signal. Conversion completions are indicated by a status bit and an interrupt (if
enabled). The resulting 10 or 12-bit data word is latched into two SFRs upon completion of a conversion. The data
can be right or left justified in these registers under software control.

Window Compare registers for the ADC data can be configured to interrupt the controller when ADC data is within
or outside of a specified range. The ADC can monitor a key voltage continuously in background mode, but not inter-
rupt the controller unless the converted data is within the specified window.

12-Bit

SAR

ADC

+
-

TEMP

SENSOR

9-to-1

AMUX
(SE or

DIFF)

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

AV+

Programmable Gain

Amplifier

Analog Multiplexer

Window Compare

Logic

ADC Data

Registers

Window

Compare

Interrupt

Conversion

Complete

Interrupt

Configuration, Control, and Data

Registers

Start
Conversion

Timer 3 Overflow

Timer 2 Overflow

Writ e t o AD0BUSY

CNVSTR0

External VREF

DAC0 Output

VREF

AGND

Figure 1.11. 12-Bit ADC Block Diagram

Page 34

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.9.

8-Bit Analog to Digital Converter

The C8051F12x Family have an on-board 8-bit SAR ADC (ADC2) with an 8-channel input multiplexer and pro-
grammable gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit linearity with an INL of
±1LSB. Eight input pins are available for measurement. The ADC is under full control of the CIP-51 microcontroller
via the Special Function Registers. The ADC2 voltage reference is selected between the analog power supply (AV+)
and an external VREF pin. On C8051F120/2/4/6 devices, ADC2 has its own dedicated VREF2 input pin; on
C8051F121/3/5/7 devices, ADC2 shares the VREFA input pin with the 12/10-bit ADC0. User software may put
ADC2 into shutdown mode to save power.

A programmable gain amplifier follows the analog multiplexer. The gain stage can be especially useful when differ-
ent ADC input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal
with a large DC offset (in differential mode, a DAC could be used to provide the DC offset). The PGA gain can be set
in software to 0.5, 1, 2, or 4.

A flexible conversion scheduling system allows ADC2 conversions to be initiated by software commands, timer
overflows, or an external input signal. ADC2 conversions may also be synchronized with ADC0 software-com-
manded conversions. Conversion completions are indicated by a status bit and an interrupt (if enabled), and the
resulting 8-bit data word is latched into an SFR upon completion.

+
-

AV+

8-to-1

AMUX

AIN2.0

AIN2.1

AIN2.2

AIN2.3

AIN2.4

AIN2.5

AIN2.6

AIN2.7

Configuration, Control, and Data Registers

Programmable Gain

Amplifier

Analog Multiplexer

8-Bit
SAR

ADC

Start Conversion

Timer 3 Overflow

Timer 2 Overflow

Write to AD2BUSY

CNVSTR2 Input

Write to AD0BUSY
(synchronized with
ADC0)

ADC Data

Conversion

Complete

Interrupt

External VREF

AV+

VREF

Window

Compare

Logic

Window

Compare

Interrupt

Figure 1.12. 8-Bit ADC Diagram

DS008-1.1-JUN03

Page 35

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

1.10.

Comparators and DACs

Each C8051F12x MCU has two 12-bit DACs and two comparators on chip. The MCU data and control interface to
each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low
power shutdown mode.

The comparators have software programmable hysteresis and response time. The response time of the comparators
can be adjusted to minimize power consumption, or to maximize speed. Each comparator can generate an interrupt on
its rising edge, falling edge, or both; these interrupts are capable of waking up the MCU from sleep mode. The com-
parators' output state can also be polled in software. The comparator outputs can be programmed to appear on the Port
I/O pins via the Crossbar.

The DACs are voltage output mode, and include a flexible output scheduling mechanism. This scheduling mecha-
nism allows DAC output updates to be forced by a software write or a Timer 2, 3, or 4 overflow. The DAC voltage
reference is supplied via the dedicated VREFD input pin on C8051F120/2/4/6 devices or via the internal voltage ref-
erence on C8051F121/3/5/7 devices. The DACs are useful as references for the comparators or offsets for the differ-
ential inputs of the ADC.

CP1

CP1+

CP1-

DAC0

DAC1

REF

CP0

CIP-51

and

Interrupt

Handler

CP1

DAC0

DAC1

CP0+

CP0-

CP1

CP0

(Port I/O)

CP0

SFR's

(Data

and

Cntrl)

CROSSBAR

Figure 1.13. Comparator and DAC Diagram

Page 36

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

ABSOLUTE MAXIMUM RATINGS

Table 2.1. Absolute Maximum Ratings

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Ambient temperature under bias

-55

125

°C

Storage Temperature

-65

150

°C

Voltage on any Pin (except VDD and Port I/O) with
respect to DGND

-0.3

VDD +

0.3

Voltage on any Port I/O Pin or /RST with respect to
DGND

-0.3

5.8

Voltage on VDD with respect to DGND

-0.3

4.2

Maximum Total current through VDD, AV+, DGND,
and AGND

800

Maximum output current sunk by any Port pin

100

Maximum output current sunk by any other I/O pin

Maximum output current sourced by any Port pin

100

Maximum output current sourced by any other I/O pin

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This

is a stress rating only and functional operation of the devices at those or any other conditions above those indicated
in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

DS008-1.1-JUN03

Page 37

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

GLOBAL DC ELECTRICAL CHARACTERISTICS

Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3)

-40°C TO +85°C, 100 MHZ SYSTEM CLOCK UNLESS OTHERWISE SPECIFIED.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Analog Supply Voltage (Note 1) SYSCLK = 0 to 50 MHz

SYSCLK > 50 MHz

2.7
3.0

3.0
3.3

3.6
3.6

V
V

Analog Supply Current

Internal REF, ADC, DAC, Compar-
ators all active

1.7

TBD

Analog Supply Current with
analog sub-systems inactive

Internal REF, ADC, DAC, Compar-
ators all disabled, oscillator disabled

0.2

TBD

µA

Analog-to-Digital Supply Delta
(|VDD - AV+|)

0.5

Digital Supply Voltage

SYSCLK = 0 to 50 MHz
SYSCLK > 50 MHz

2.7
3.0

3.0
3.3

3.6
3.6

V
V

Digital Supply Current with
CPU active

VDD=3.0 V, Clock=100 MHz
VDD=2.7 V, Clock=50 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz

TBD

0.6

mA
mA
mA

µA

Digital Supply Current with
CPU inactive (not accessing
FLASH)

VDD=3.0 V, Clock=100 MHz
VDD=2.7 V, Clock=50 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz

TBD
TBD
TBD
TBD

mA
mA
mA

µA

Digital Supply Current (shut-
down)

Oscillator not running

TBD

µA

Digital Supply RAM Data
Retention Voltage

1.5

SYSCLK (System Clock)
(Notes 2 and 3)

VDD, AV+ = 2.7 V to 3.6 V
VDD, AV+ = 3.0 V to 3.6 V

0
0

100

MHz
MHz

Specified Operating Tempera-
ture Range

-40

+85

°C

Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
Note 2: SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be

derived from the Phase-Locked Loop (PLL).

Note 3: SYSCLK must be at least 32 kHz to enable debugging.

Page 38

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)

-40°C TO +85°C, 50 MHZ SYSTEM CLOCK UNLESS OTHERWISE SPECIFIED.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Analog Supply Voltage

(Note 1)

2.7

3.0

3.6

Analog Supply Current

Internal REF, ADC, DAC, Compar-
ators all active

1.7

TBD

Analog Supply Current with
analog sub-systems inactive

Internal REF, ADC, DAC, Compar-
ators all disabled, oscillator disabled

0.2

TBD

µA

Analog-to-Digital Supply Delta
(|VDD - AV+|)

0.5

Digital Supply Voltage

2.7

3.0

3.6

Digital Supply Current with
CPU active

VDD=2.7 V, Clock=50 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz

0.6

mA
mA

µA

Digital Supply Current with
CPU inactive (not accessing
FLASH)

VDD=2.7 V, Clock=50 MHz
VDD=2.7 V, Clock=1 MHz
VDD=2.7 V, Clock=32 kHz

0.3

TBD

mA
mA

µA

Digital Supply Current (shut-
down)

Oscillator not running

0.4

µA

Digital Supply RAM Data
Retention Voltage

1.5

SYSCLK (System Clock)
(Notes 2 and 3)

MHz

Specified Operating Tempera-
ture Range

-40

+85

°C

Note 1: Analog Supply AV+ must be greater than 1 V for VDD monitor to operate.
Note 2: SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be

derived from the Phase-Locked Loop (PLL).

Note 3: SYSCLK must be at least 32 kHz to enable debugging.

DS008-1.1-JUN03

Page 39

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

PINOUT AND PACKAGE DEFINITIONS

Table 4.1. Pin Definitions

Name

Pin Numbers

Type

Description

F120/

2/4/6

F121/

3/5/7

VDD

37, 64,

24, 41,

Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.

DGND

38, 63,

25, 40,

Digital Ground. Must be tied to Ground.

AV+

11, 14

Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.

AGND

10, 13

Analog Ground. Must be tied to Ground.

TMS

D In

JTAG Test Mode Select with internal pull-up.

TCK

D In

JTAG Test Clock with internal pull-up.

TDI3

D I

JTAG Test Data I

nput with internal pull-up. TDI

is latched on the

rising edge of TCK.

TDO

D Out JTAG Test Data Output with internal pull-up. Data is shifted out on

TDO on the falling edge of TCK. TDO output is a tri-state driver.

/RST

D I/O

Device Reset. Open-drain output of internal VDD monitor. Is driven
low when VDD is < V

RST

and MONEN is high. An external source

can initiate a system reset by driving this pin low.

XTAL1

A In

Crystal Input. This pin is the return for the internal oscillator circuit
for a crystal or ceramic resonator. For a precision internal clock,
connect a crystal or ceramic resonator from XTAL1 to XTAL2. If
overdriven by an external CMOS clock, this becomes the system
clock.

XTAL2

A Out Crystal Output. This pin is the excitation driver for a crystal or

ceramic resonator.

MONEN

D In

VDD Monitor Enable. When tied high, this pin enables the internal
VDD monitor, which forces a system reset when VDD is < V

RST

When tied low, the internal VDD monitor is disabled.
This pin must be tied high or low.

VREF

A I/O

Bandgap Voltage Reference Output (all devices).
DAC Voltage Reference Input (C8051F121/3/5/7 only).

VREFA

A In

ADC0 and ADC2 Voltage Reference Input.

VREF0

A In

ADC0 Voltage Reference Input.

VREF2

A In

ADC2 Voltage Reference Input.

VREFD

A In

DAC Voltage Reference Input.

Page 40

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

AIN0.0

A In

ADC0 Input Channel 0 (See ADC0 Specification for complete
description).

AIN0.1

A In

ADC0 Input Channel 1 (See ADC0 Specification for complete
description).

AIN0.2

A In

ADC0 Input Channel 2 (See ADC0 Specification for complete
description).

AIN0.3

A In

ADC0 Input Channel 3 (See ADC0 Specification for complete
description).

AIN0.4

A In

ADC0 Input Channel 4 (See ADC0 Specification for complete
description).

AIN0.5

A In

ADC0 Input Channel 5 (See ADC0 Specification for complete
description).

AIN0.6

A In

ADC0 Input Channel 6 (See ADC0 Specification for complete
description).

AIN0.7

A In

ADC0 Input Channel 7 (See ADC0 Specification for complete
description).

CP0+

A In

Comparator 0 Non-Inverting Input.

CP0-

A In

Comparator 0 Inverting Input.

CP1+

A In

Comparator 1 Non-Inverting Input.

CP1-

A In

Comparator 1 Inverting Input.

DAC0

100

A Out Digital to Analog Converter 0 Voltage Output. (See DAC Specifica-

tion for complete description).

DAC1

A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specifica-

tion for complete description).

P0.0

D I/O

Port 0.0. See Port Input/Output section for complete description.

P0.1

D I/O

Port 0.1. See Port Input/Output section for complete description.

P0.2

D I/O

Port 0.2. See Port Input/Output section for complete description.

P0.3

D I/O

Port 0.3. See Port Input/Output section for complete description.

P0.4

D I/O

Port 0.4. See Port Input/Output section for complete description.

ALE/P0.5

D I/O

ALE Strobe for External Memory Address bus (multiplexed mode)
Port 0.5
See Port Input/Output section for complete description.

Table 4.1. Pin Definitions

Name

Pin Numbers

Type

Description

F120/

2/4/6

F121/

3/5/7

DS008-1.1-JUN03

Page 41

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

/RD/P0.6

D I/O

/RD Strobe for External Memory Address bus
Port 0.6
See Port Input/Output section for complete description.

/WR/P0.7

D I/O

/WR Strobe for External Memory Address bus
Port 0.7
See Port Input/Output section for complete description.

AIN2.0/A8/P1.0

A In

D I /O

ADC2 Input Channel 0 (See ADC2 Specification for complete
description).
Bit 8 External Memory Address bus (Non-multiplexed mode)
Port 1.0
See Port Input/Output section for complete description.

AIN2.1/A9/P1.1

A In

D I /O

Port 1.1. See Port Input/Output section for complete description.

AIN2.2/A10/P1.2

A In

D I /O

Port 1.2. See Port Input/Output section for complete description.

AIN2.3/A11/P1.3

A In

D I /O

Port 1.3. See Port Input/Output section for complete description.

AIN2.4/A12/P1.4

A In

D I /O

Port 1.4. See Port Input/Output section for complete description.

AIN2.5/A13/P1.5

A In

D I /O

Port 1.5. See Port Input/Output section for complete description.

AIN2.6/A14/P1.6

A In

D I /O

Port 1.6. See Port Input/Output section for complete description.

AIN2.7/A15/P1.7

A In

D I /O

Port 1.7. See Port Input/Output section for complete description.

A8m/A0/P2.0

D I/O

Bit 8 External Memory Address bus (Multiplexed mode)
Bit 0 External Memory Address bus (Non-multiplexed mode)
Port 2.0
See Port Input/Output section for complete description.

A9m/A1/P2.1

D I/O

Port 2.1. See Port Input/Output section for complete description.

A10m/A2/P2.2

D I/O

Port 2.2. See Port Input/Output section for complete description.

A11m/A3/P2.3

D I/O

Port 2.3. See Port Input/Output section for complete description.

A12m/A4/P2.4

D I/O

Port 2.4. See Port Input/Output section for complete description.

A13m/A5/P2.5

D I/O

Port 2.5. See Port Input/Output section for complete description.

A14m/A6/P2.6

D I/O

Port 2.6. See Port Input/Output section for complete description.

Table 4.1. Pin Definitions

Name

Pin Numbers

Type

Description

F120/

2/4/6

F121/

3/5/7

Page 42

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

A15m/A7/P2.7

D I/O

Port 2.7. See Port Input/Output section for complete description.

AD0/D0/P3.0

D I/O

Bit 0 External Memory Address/Data bus (Multiplexed mode)
Bit 0 External Memory Data bus (Non-multiplexed mode)
Port 3.0
See Port Input/Output section for complete description.

AD1/D1/P3.1

D I/O

Port 3.1. See Port Input/Output section for complete description.

AD2/D2/P3.2

D I/O

Port 3.2. See Port Input/Output section for complete description.

AD3/D3/P3.3

D I/O

Port 3.3. See Port Input/Output section for complete description.

AD4/D4/P3.4

D I/O

Port 3.4. See Port Input/Output section for complete description.

AD5/D5/P3.5

D I/O

Port 3.5. See Port Input/Output section for complete description.

AD6/D6/P3.6

D I/O

Port 3.6. See Port Input/Output section for complete description.

AD7/D7/P3.7

D I/O

Port 3.7. See Port Input/Output section for complete description.

P4.0

D I/O

Port 4.0. See Port Input/Output section for complete description.

P4.1

D I/O

Port 4.1. See Port Input/Output section for complete description.

P4.2

D I/O

Port 4.2. See Port Input/Output section for complete description.

P4.3

D I/O

Port 4.3. See Port Input/Output section for complete description.

P4.4

D I/O

Port 4.4. See Port Input/Output section for complete description.

ALE/P4.5

D I/O

ALE Strobe for External Memory Address bus (multiplexed mode)
Port 4.5
See Port Input/Output section for complete description.

/RD/P4.6

D I/O

/RD Strobe for External Memory Address bus
Port 4.6
See Port Input/Output section for complete description.

/WR/P4.7

D I/O

/WR Strobe for External Memory Address bus
Port 4.7
See Port Input/Output section for complete description.

A8/P5.0

D I/O

Bit 8 External Memory Address bus (Non-multiplexed mode)
Port 5.0
See Port Input/Output section for complete description.

A9/P5.1

D I/O

Port 5.1. See Port Input/Output section for complete description.

A10/P5.2

D I/O

Port 5.2. See Port Input/Output section for complete description.

A11/P5.3

D I/O

Port 5.3. See Port Input/Output section for complete description.

Table 4.1. Pin Definitions

Name

Pin Numbers

Type

Description

F120/

2/4/6

F121/

3/5/7

DS008-1.1-JUN03

Page 43

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

A12/P5.4

D I/O

Port 5.4. See Port Input/Output section for complete description.

A13/P5.5

D I/O

Port 5.5. See Port Input/Output section for complete description.

A14/P5.6

D I/O

Port 5.6. See Port Input/Output section for complete description.

A15/P5.7

D I/O

Port 5.7. See Port Input/Output section for complete description.

A8m/A0/P6.0

D I/O

Bit 8 External Memory Address bus (Multiplexed mode)
Bit 0 External Memory Address bus (Non-multiplexed mode)
Port 6.0
See Port Input/Output section for complete description.

A9m/A1/P6.1

D I/O

Port 6.1. See Port Input/Output section for complete description.

A10m/A2/P6.2

D I/O

Port 6.2. See Port Input/Output section for complete description.

A11m/A3/P6.3

D I/O

Port 6.3. See Port Input/Output section for complete description.

A12m/A4/P6.4

D I/O

Port 6.4. See Port Input/Output section for complete description.

A13m/A5/P6.5

D I/O

Port 6.5. See Port Input/Output section for complete description.

A14m/A6/P6.6

D I/O

Port 6.6. See Port Input/Output section for complete description.

A15m/A7/P6.7

D I/O

Port 6.7. See Port Input/Output section for complete description.

AD0/D0/P7.0

D I/O

Bit 0 External Memory Address/Data bus (Multiplexed mode)
Bit 0 External Memory Data bus (Non-multiplexed mode)
Port 7.0
See Port Input/Output section for complete description.

AD1/D1/P7.1

D I/O

Port 7.1. See Port Input/Output section for complete description.

AD2/D2/P7.2

D I/O

Port 7.2. See Port Input/Output section for complete description.

AD3/D3/P7.3

D I/O

Port 7.3. See Port Input/Output section for complete description.

AD4/D4/P7.4

D I/O

Port 7.4. See Port Input/Output section for complete description.

AD5/D5/P7.5

D I/O

Port 7.5. See Port Input/Output section for complete description.

AD6/D6/P7.6

D I/O

Port 7.6. See Port Input/Output section for complete description.

AD7/D7/P7.7

D I/O

Port 7.7. See Port Input/Output section for complete description.

Table 4.1. Pin Definitions

Name

Pin Numbers

Type

Description

F120/

2/4/6

F121/

3/5/7

Page 44

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

C8051F120
C8051F122
C8051F124
C8051F126

AD6/D6/P7.6

AD7/D7/P7.7

VDD

DGND

P0.0

P0.1

P0.2

P0.3

P0.4

ALE/P0.5

/RD/P0.6

/WR/P0.7

AD0/D0/P3.0

AD1/D1/P3.1

AD2/D2/P3.2

AD3/D3/P3.3

A13m/A5/P6.5

A14m/A6/P6.6

A15m/A7/P6.7

AD0/D0/P7.0

AD1/D1/P7.1

AD2/D2/P7.2

AD3/D3/P7.3

AD4/D4/P7.4

AD5/D5/P7.5

.
0

.
1

.
2

.
3

.
4

/
P4

.
5

/RD

/
P4.6

/WR/P4.

/
P

.
0

/
P

.
1

/
P

.
2

/
P

.
3

/
P

.
4

/
P

.
5

/
P

.
6

/
P

.
7

/
A

/
P

.
0

/
A

/
P

.
1

0m/A2/

P6.2

1m/A3/

P6.3

2m/A4/

P6.4

AGND

AV+

VREF

AGND

AV+

VREFD

VREF0

VREF2

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TMS

TCK

TDI

TDO

/RST

CP1-

CP1+

CP0-

CP0+

NEN

I
N

.
7

/A1

/P1

.
7

I
N

.
6

/A1

/P1

.
6

I
N

.
5

/A1

/P1

.
5

I
N

.
4

/A1

/P1

.
4

I
N

.
3

/A1

/P1

.
3

I
N

.
2

/A1

/P1

.
2

I
N

.1/A

9/P1

I
N

.0/A

8/P1

A15

/
A

7/P

A14

/
A

6/P

A13

/
A

5/P

A12

/
A

4/P

A11

/
A

3/P

A10

/
A

2/P

/
A1/P

2.1

/
A0/P

2.0

7/D

/P3

.
7

6/D

/P3

.
6

5/D

/P3

.
5

4/D

/P3

.
4

Figure 4.1. TQFP-100 Pinout Diagram

Page 46

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

C8051F121
C8051F123
C8051F125
C8051F127

TDO

TDI

TCK

TMS

.
0

.
1

.
2

.
3

.
4

.
5

D/P0

/WR/P0.7

AD0/D0/P3.0

AD1/D1/P3.1

AD2/D2/P3.2

AD3/D3/P3.3

AD4/D4/P3.4

AD5/D5/P3.5

VDD

DGND

AD6/D6/P3.6

AD7/D7/P3.7

A8m/A0/P2.0

A9m/A1/P2.1

A10m/A2/P2.2

A11m/A3/P2.3

A12m/A4/P2.4

CP1-

CP1+

CP0-

CP0+

AGND

AV+

VREF

VREFA

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

XTA

MONE

AIN

/P1

.
7

AIN

/P1

.
6

AIN

/P1

.
5

AIN

/P1

.
4

AIN

/P1

.
3

AIN

/P1

.
2

I
N2

.1/

/
P1

I
N2

.0/

/
P1

/
A

.
7

/
A

.
6

/
A

.
5

Figure 4.3. TQFP-64 Pinout Diagram

DS008-1.1-JUN03

Page 49

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY)

The ADC0 subsystem for the C8051F120/1/4/5 consists of a 9-channel, configurable analog multiplexer (AMUX0), a
programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated
track-and-hold and Programmable Window Detector (see block diagram in Figure 5.1). The AMUX0, PGA0, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ters shown in Figure 5.1. The voltage reference used by ADC0 is selected as described in

Section "9. VOLTAGE

REFERENCE (C8051F120/2/4/6)" on page 107

for C8051F120/2/4/6 devices, or

Section "10. VOLTAGE REF-

ERENCE (C8051F121/3/5/7)" on page 109

for C8051F121/3/5/7 devices. The ADC0 subsystem (ADC0, track-

and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1.
The ADC0 subsystem is in low power shutdown when this bit is logic 0.

5.1.

Analog Multiplexer and PGA

Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected
to an on-chip temperature sensor (temperature transfer function is shown in Figure 5.2). AMUX input pairs can be
programmed to operate in either differential or single-ended mode. This allows the user to select the best measure-
ment technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to
all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register
AMX0SL (Figure 5.6), and the Configuration register AMX0CF (Figure 5.5). The table in Figure 5.6 shows AMUX
functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount
determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 5.7). The
PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.

12-Bit

SAR

ADC

+
-

AV+

TEMP

SENSOR

9-to-1

AMUX
(SE or

DIFF)

AV+

AD0EN

YSC

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

Start Conversion

AGND

DC0

ADC0LTL

ADC0LTH

ADC0GTL

ADC0GTH

Timer 3 Overflow

Timer 2 Overflow

AD0BUSY (W)

CNVSTR0

AD0WINT

Comb.

Logic

AMX0CF

AMX0SL

AMX0

AD0

AMX0

AD1

AMX0

AD2

AMX0

AD3

I
C

ADC0CF

AMP

ADC0CN

0LJ

AD0

INT

USY

I
N

AD0

Figure 5.1. 12-Bit ADC0 Functional Block Diagram

DS008-1.1-JUN03

Page 51

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

5.2.

ADC Modes of Operation

ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock
divided by the value held in the ADCSC bits of register ADC0CF.

5.2.1.

Starting a Conversion

A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conver-
sion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by:

Writing a `1' to the AD0BUSY bit of ADC0CN;

A Timer 3 overflow (i.e. timed continuous conversions);

A rising edge detected on the external ADC convert start signal, CNVSTR0;

A Timer 2 overflow (i.e. timed continuous conversions).

The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. The fall-
ing edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag (ADC0CN.5). Con-
verted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be
either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 5.11) depending on the pro-
grammed state of the AD0LJST bit in the ADC0CN register.

When initiating conversions by writing a `1' to AD0BUSY, the AD0INT bit should be polled to determine when a
conversion has completed (ADC0 interrupts may also be used). The recommended polling procedure is shown below.

Step 1. Write a `0' to AD0INT;
Step 2. Write a `1' to AD0BUSY;
Step 3. Poll AD0INT for `1';
Step 4. Process ADC0 data.

When CNVSTR0 is used as a conversion start source, it must be enabled in the crossbar, and the corresponding pin
must be set to open-drain, high-impedance mode (see

Section "19. PORT INPUT/OUTPUT" on page 215

for more

details on Port I/O configuration).

Page 52

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

5.2.2.

Tracking Modes

The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-
power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after
the start-of-conversion signal). When the CNVSTR0 signal is used to initiate conversions in low-power tracking
mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on the rising edge of CNVSTR0 (see
Figure 5.3). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Low-power track-and-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that
settling time requirements are met (see

Section "5.2.3. Settling Time Requirements" on page 53

10 11 12 13 14 15 16

CNVSTR0

(AD0CM[1:0]=10)

ADC0TM=1

ADC0TM=0

Timer 2, Timer 3 Overflow;

Writ e '1' t o AD0BUSY

(AD0CM[1:0]=00, 01, 11)

ADC0TM=1

ADC0TM=0

A. ADC Timing for External Trigger Source

B. ADC Timing for Internal Trigger Sources

SAR Clocks

10 11 12 13 14 15 16 17 18 19

10 11 12 13 14 15 16

SAR Clocks

Track

Convert

Low Power Mode

Low Power

or Convert

Track Or Convert

Convert

Track

Convert

Low Power Mode

Low Power

or Convert

Track or

Convert

Track

Figure 5.3. ADC0 Track and Conversion Example Timing

DS008-1.1-JUN03

Page 53

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

5.2.3.

Settling Time Requirements

When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum track-
ing time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0
MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the
conversion. Figure 5.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes.
Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given set-
tling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature Sensor output, R

TOTAL

reduces to R

MUX

. An absolute minimum settling time of 1.5 µs is required after any MUX or PGA selection. Note

that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most
applications, these three SAR clocks will meet the tracking requirements.

Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R

TOTAL

is the sum of the ADC0 MUX resistance and any external source resistance.

n is the ADC resolution in bits (12).

Equation 5.1. ADC0 Settling Time Requirements

-------

TOTAL

SAMPLE

MUX

= 5k

Input

= R

MUX

* C

SAMPLE

MUX

= 5k

SAMPLE

= 1 0pF

SAMPLE

= 1 0pF

MUX Select

Differential Mode

AIN0.x

AIN0.y

MUX

= 5k

SAMPLE

= 10pF

Input

= R

MUX

* C

SAMPLE

MUX Select

Single-Ended Mode

AIN0.x

Figure 5.4. ADC0 Equivalent Input Circuits

Page 54

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 5.5. AMX0CF: AMUX0 Configuration Register

Bits7-4:

UNUSED. Read = 0000b; Write = don't care.

Bit3:

AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit.
0: AIN0.6 and AIN0.7 are independent single-ended inputs.
1: AIN0.6, AIN0.7 are (respectively) +, - differential input pair.

Bit2:

AIN45IC: AIN0.4, AIN0.5 Input Pair Configuration Bit.
0: AIN0.4 and AIN0.5 are independent single-ended inputs.
1: AIN0.4, AIN0.5 are (respectively) +, - differential input pair.

Bit1:

AIN23IC: AIN0.2, AIN0.3 Input Pair Configuration Bit.
0: AIN0.2 and AIN0.3 are independent single-ended inputs.
1: AIN0.2, AIN0.3 are (respectively) +, - differential input pair.

Bit0:

AIN01IC: AIN0.0, AIN0.1 Input Pair Configuration Bit.
0: AIN0.0 and AIN0.1 are independent single-ended inputs.
1: AIN0.0, AIN0.1 are (respectively) +, - differential input pair.

NOTE:

The ADC0 Data Word is in 2's complement format for channels configured as differential.

SFR Page:
SFR Address:

0
0xBA

R/W

Reset Value

AIN67IC

AIN45IC

AIN23IC

AIN01IC

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 55

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 5.6. AMX0SL: AMUX0 Channel Select Register

Bits7-4:

UNUSED. Read = 0000b; Write = don't care.

Bits3-0:

AMX0AD3-0: AMX0 Address Bits.
0000-1111b: ADC Inputs selected per chart below.

SFR Page:
SFR Address:

0
0xBB

R/W

Reset Value

AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AMX0AD3-0

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

i
ts

-
0

0000

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0001

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0010

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0011

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0100

AIN0.0

AIN0.1

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0101

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0110

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0111

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

1000

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1001

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1010

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1011

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1100

AIN0.0

AIN0.1

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1101

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1110

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1111

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

DS008-1.1-JUN03

Page 57

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 5.8. ADC0CN: ADC0 Control Register

Bit7:

AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.

Bit6:

AD0TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by ADCM1-0 bits.

Bit5:

AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.

Bit4:

AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set to
logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM1-0 = 00b.

Bits3-2:

AD0CM1-0: ADC0 Start of Conversion Mode Select.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of `1' to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR0.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of `1' to AD0BUSY and lasts for 3 SAR clocks, followed by con-
version.
01: Tracking started by the overflow of Timer 3 and lasts for 3 SAR clocks, followed by conversion.
10: ADC0 tracks only when CNVSTR0 input is logic low; conversion starts on rising CNVSTR0
edge.
11: Tracking started by the overflow of Timer 2 and lasts for 3 SAR clocks, followed by conversion.

Bit1:

AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.

Bit0:

AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.

SFR Page:
SFR Address:

0
0xE8

(bit addressable)

R/W

Reset Value

AD0EN

AD0TM

AD0INT AD0BUSY AD0CM1

AD0CM0

AD0WINT

AD0LJST 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 5.11. ADC0 Data Word Example

12-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows:
ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0

(ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading, otherwise =
0000b).

ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1

(ADC0L[3:0] = 0000b).

Example: ADC0 Data Word Conversion Map, AIN0.0 Input in Single-Ended Mode

(AMX0CF = 0x00, AMX0SL = 0x00)

Example: ADC0 Data Word Conversion Map, AIN0.0-AIN0.1 Differential Input Pair

(AMX0CF = 0x01, AMX0SL = 0x00)

For AD0LJST = 0:

; `n' = 12 for Single-Ended; `n'=11 for Differential.

AIN0.0-AGND

(Volts)

ADC0H:ADC0L

(AD0LJST = 0)

ADC0H:ADC0L

(AD0LJST = 1)

VREF * (4095/4096)

0x0FFF

0xFFF0

VREF / 2

0x0800

0x8000

VREF * (2047/4096)

0x07FF

0x7FF0

0x0000

AIN0.0-AIN0.1

(Volts)

ADC0H:ADC0L

(AD0LJST = 0)

ADC0H:ADC0L

(AD0LJST = 1)

VREF * (2047/2048)

0x07FF

0x7FF0

VREF / 2

0x0400

0x4000

VREF * (1/2048)

0x0001

0x0010

0x0000

-VREF * (1/2048)

0xFFFF (-1d)

0xFFF0

-VREF / 2

0xFC00 (-1024d)

0xC000

-VREF

0xF800 (-2048d)

0x8000

Code

Vin

Gain

VREF

---------------

Page 60

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

5.3.

ADC0 Programmable Window Detector

The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits,
and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven
system, saving code space and CPU bandwidth while delivering faster system response times. The window detector
interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The high and low bytes of the reference
words are loaded into the ADC0 Greater-Than and ADC0 Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH,
and ADC0LTL). Reference comparisons are shown starting on page 62. Notice that the window detector flag can be
asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of
the ADC0GTx and ADC0LTx registers.

Figure 5.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register

Bits7-0:

High byte of ADC0 Greater-Than Data Word.

SFR Page:
SFR Address:

0
0xC5

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Figure 5.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register

Bits7-0:

Low byte of ADC0 Greater-Than Data Word.

SFR Page:
SFR Address:

0
0xC4

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Page 62

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data

Given:
AMX0SL = 0x00, AMX0CF = 0x00
AD0LJST = `0',
ADC0LTH:ADC0LTL = 0x0200,
ADC0GTH:ADC0GTL = 0x0100.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x0200 and
> 0x0100.

Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = `0',
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0x0200.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is > 0x0200 or
< 0x0100.

0x0FFF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

AD0WINT=1

AD0WINT
notaffected

ADC Data

Word

0x0FFF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

AD0WINT=1

AD0WINT
notaffected

AD0WINT=1

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC0GTH:ADC0GTL

ADC0LTH:ADC0LTL

InputVoltage

(AD0.0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

InputVoltage

(AD0.0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0x07FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xF800

AD0WINT=1

AD0WINT
notaffected

0x07FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xF800

AD0WINT=1

AD0WINT
notaffected

-REF

InputVoltage

(AD0.0 - AD0.1)

AD0WINT=1

REF x (2047/2048)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (256/2048)

REF x (-1/2048)

-REF

InputVoltage

(AD0.0 - AD0.1)

REF x (2047/2048)

REF x (256/2048)

REF x (-1/2048)

Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `0',
ADC0LTH:ADC0LTL = 0x0100,
ADC0GTH:ADC0GTL = 0xFFFF.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x0100 and
> 0xFFFF. (In two's-complement math,
0xFFFF = -1.)

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `0',
ADC0LTH:ADC0LTL = 0xFFFF,
ADC0GTH:ADC0GTL = 0x0100.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0xFFFF or
> 0x0100. (In two's-complement math,
0xFFFF = -1.)

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DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

AD0WINT=1

AD0WINT
notaffected

ADC Data

Word

0xFFF0

0x2010

0x2000

0x1FF0

0x1010

0x1000

0x0FF0

0x0000

AD0WINT=1

AD0WINT
notaffected

AD0WINT=1

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC0GTH:ADC0GTL

ADC0LTH:ADC0LTL

InputVoltage

(AD0.0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

InputVoltage

(AD0.0 - AGND)

REF x (4095/4096)

REF x (256/4096)

REF x (512/4096)

Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data

Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = `1',
ADC0LTH:ADC0LTL = 0x2000,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x2000 and
> 0x1000.

Given:
AMX0SL = 0x00, AMX0CF = 0x00,
AD0LJST = `1'
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0x2000.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x1000 or
> 0x2000.

DS008-1.1-JUN03

Page 65

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0x7FF0

0x1010

0x1000

0x0FF0

0x0000

0xFFF0

0xFFE0

0x8000

AD0WINT=1

AD0WINT
notaffected

0x7FF0

0x1010

0x1000

0x0FF0

0x0000

0xFFF0

0xFFE0

0x8000

AD0WINT=1

AD0WINT
notaffected

-REF

InputVoltage

(AD0.0 - AD0.1)

AD0WINT=1

REF x (2047/2048)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (256/2048)

REF x (-1/2048)

-REF

InputVoltage

(AD0.0 - AD0.1)

REF x (2047/2048)

REF x (256/2048)

REF x (-1/2048)

Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `1',
ADC0LTH:ADC0LTL = 0x1000,
ADC0GTH:ADC0GTL = 0xFFF0.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x1000 and
> 0xFFF0. (Two's-complement math.)

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `1',
ADC0LTH:ADC0LTL = 0xFFF0,
ADC0GTH:ADC0GTL = 0x1000.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0xFFF0 or
> 0x1000. (Two's-complement math.)

Page 66

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/5)

VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution

bits

Integral Nonlinearity

±1

LSB

Differential Nonlinearity

Guaranteed Monotonic

±1

LSB

Offset Error

-3±1

LSB

Full Scale Error

Differential mode

-7±3

LSB

Offset Temperature Coefficient

±0.25

ppm/°C

DYNAMIC PERFORMANCE (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps

Signal-to-Noise Plus Distortion

Total Harmonic Distortion

Up to the 5

harmonic

-75

Spurious-Free Dynamic Range

CONVERSION RATE

SAR Clock Frequency

2.5

MHz

Conversion Time in SAR Clocks

clocks

Track/Hold Acquisition Time

1.5

µs

Throughput Rate

100

ksps

ANALOG INPUTS

Input Voltage Range

Single-ended operation

VREF

*Common-mode Voltage Range

Differential operation

AGND

AV+

Input Capacitance

TEMPERATURE SENSOR

Linearity

Note 1

±0.2

°C

Gain

Note 2

2.86

±0.034

mV / °C

Offset

Note 1, Note 2, (Temp = 0 °C)

776

±8.5

POWER SPECIFICATIONS

Power Supply Current (AV+ sup-
plied to ADC)

Operating Mode, 100 ksps

450

900

µA

Power Supply Rejection

±0.3

mV/V

Note 1: Includes ADC offset, gain, and linearity variations.
Note 2: Represents one standard deviation from the mean.

DS008-1.1-JUN03

Page 67

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

ADC0 (10-BIT ADC, C8051F122/3/6/7 ONLY)

The ADC0 subsystem for the C8051F122/3/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX0), a
programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and Programmable Window Detector (see block diagram in Figure 6.1). The AMUX0, PGA0, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in

Section "9. VOLTAGE

REFERENCE (C8051F120/2/4/6)" on page 107

for C8051F120/2/4/6 devices, or

Section "10. VOLTAGE REF-

ERENCE (C8051F121/3/5/7)" on page 109

for C8051F121/3/5/7 devices. The ADC0 subsystem (ADC0, track-

and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1.
The ADC0 subsystem is in low power shutdown when this bit is logic 0.

6.1.

Analog Multiplexer and PGA

Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected
to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX input pairs can be
programmed to operate in either differential or single-ended mode. This allows the user to select the best measure-
ment technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to
all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register
AMX0SL (Figure 6.6), and the Configuration register AMX0CF (Figure 6.5). The table in Figure 6.6 shows AMUX
functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount
determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 6.7). The
PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.

10-Bit

SAR

ADC

+
-

AV+

TEMP

SENSOR

9-to-1

AMUX
(SE or

DIFF)

AV+

AD0EN

YSC

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

Start Conversion

AGND

DC0

ADC0LTL

ADC0LTH

ADC0GTL

ADC0GTH

Timer 3 Overflow

Timer 2 Overflow

AD0BUSY (W)

CNVSTR0

AD0WINT

Comb.

Logic

AMX0SL

AMX0

AD0

AMX0

AD1

AMX0

AD2

AMX0

AD3

AMX0CF

I
C

ADC0CF

AMP

ADC0CN

0LJ

AD0

INT

USY

I
N

Figure 6.1. 10-Bit ADC0 Functional Block Diagram

DS008-1.1-JUN03

Page 69

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

6.2.

ADC Modes of Operation

ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the system clock
divided by the value held in the ADCSC bits of register ADC0CF.

6.2.1.

Starting a Conversion

A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start of Conver-
sion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by:

Writing a `1' to the AD0BUSY bit of ADC0CN;

A Timer 3 overflow (i.e. timed continuous conversions);

A rising edge detected on the external ADC convert start signal, CNVSTR0;

A Timer 2 overflow (i.e. timed continuous conversions).

The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete. The fall-
ing edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag (ADC0CN.5). Con-
verted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L. Converted data can be
either left or right justified in the ADC0H:ADC0L register pair (see example in Figure 6.11) depending on the pro-
grammed state of the AD0LJST bit in the ADC0CN register.

Step 1. Write a `0' to AD0INT;
Step 2. Write a `1' to AD0BUSY;
Step 3. Poll AD0INT for `1';
Step 4. Process ADC0 data.

When CNVSTR0 is used as a conversion start source, it must be enabled in the crossbar, and the corresponding pin
must be set to open-drain, high-impedance mode (see

Section "19. PORT INPUT/OUTPUT" on page 215

for more

details on Port I/O configuration).

Page 70

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

6.2.2.

Tracking Modes

The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-
power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after
the start-of-conversion signal). When the CNVSTR0 signal is used to initiate conversions in low-power tracking
mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on the rising edge of CNVSTR0 (see
Figure 6.3). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Low-power track-and-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that
settling time requirements are met (see

Section "6.2.3. Settling Time Requirements" on page 71

10 11 12 13 14 15 16

CNVSTR0

(AD0CM[1:0]=10)

ADC0TM=1

ADC0TM=0

Timer 2, Timer 3 Overflow;

Writ e '1' t o AD0BUSY

(AD0CM[1:0]=00, 01, 11)

ADC0TM=1

ADC0TM=0

A. ADC Timing for External Trigger Source

B. ADC Timing for Internal Trigger Sources

SAR Clocks

10 11 12 13 14 15 16 17 18 19

10 11 12 13 14 15 16

SAR Clocks

Track

Convert

Low Power Mode

Low Power

or Convert

Track Or Convert

Convert

Track

Convert

Low Power Mode

Low Power

or Convert

Track or

Convert

Track

Figure 6.3. ADC0 Track and Conversion Example Timing

DS008-1.1-JUN03

Page 71

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

6.2.3.

Settling Time Requirements

When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum track-
ing time is required before an accurate conversion can be performed. This tracking time is determined by the ADC0
MUX resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the
conversion. Figure 6.4 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes.
Notice that the equivalent time constant for both input circuits is the same. The required settling time for a given set-
tling accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output, R

TOTAL

reduces to R

MUX

. An absolute minimum settling time of 1.5 µs is required after any MUX or PGA selection. Note

that in low-power tracking mode, three SAR clocks are used for tracking at the start of every conversion. For most
applications, these three SAR clocks will meet the tracking requirements.

Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R

TOTAL

is the sum of the ADC0 MUX resistance and any external source resistance.

n is the ADC resolution in bits (10).

Equation 6.1. ADC0 Settling Time Requirements

-------

TOTAL

SAMPLE

MUX

= 5k

Input

= R

MUX

* C

SAMPLE

MUX

= 5k

SAMPLE

= 1 0pF

SAMPLE

= 1 0pF

MUX Select

Differential Mode

AIN0.x

AIN0.y

MUX

= 5k

SAMPLE

= 10pF

Input

= R

MUX

* C

SAMPLE

MUX Select

Single-Ended Mode

AIN0.x

Figure 6.4. ADC0 Equivalent Input Circuits

Page 72

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.5. AMX0CF: AMUX0 Configuration Register

Bits7-4:

UNUSED. Read = 0000b; Write = don't care.

Bit3:

AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit.
0: AIN0.6 and AIN0.7 are independent single-ended inputs.
1: AIN0.6, AIN0.7 are (respectively) +, - differential input pair.

Bit2:

AIN45IC: AIN0.4, AIN0.5 Input Pair Configuration Bit.
0: AIN0.4 and AIN0.5 are independent single-ended inputs.
1: AIN0.4, AIN0.5 are (respectively) +, - differential input pair.

Bit1:

AIN23IC: AIN0.2, AIN0.3 Input Pair Configuration Bit.
0: AIN0.2 and AIN0.3 are independent single-ended inputs.
1: AIN0.2, AIN0.3 are (respectively) +, - differential input pair.

Bit0:

AIN01IC: AIN0.0, AIN0.1 Input Pair Configuration Bit.
0: AIN0.0 and AIN0.1 are independent single-ended inputs.
1: AIN0.0, AIN0.1 are (respectively) +, - differential input pair.

NOTE:

The ADC0 Data Word is in 2's complement format for channels configured as differential.

SFR Page:
SFR Address:

0
0xBA

R/W

Reset Value

AIN67IC

AIN45IC

AIN23IC

AIN01IC

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 73

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.6. AMX0SL: AMUX0 Channel Select Register

Bits7-4:

UNUSED. Read = 0000b; Write = don't care.

Bits3-0:

AMX0AD3-0: AMX0 Address Bits.
0000-1111b: ADC Inputs selected per chart below.

SFR Page:
SFR Address:

0
0xBB

R/W

Reset Value

AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AMX0AD3-0

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

i
ts

-
0

0000

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0001

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0010

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0011

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

AIN0.6

AIN0.7

TEMP

SENSOR

0100

AIN0.0

AIN0.1

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0101

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0110

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

0111

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

AIN0.6

AIN0.7

TEMP

SENSOR

1000

AIN0.0

AIN0.1

AIN0.2

AIN0.3

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1001

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1010

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1011

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

AIN0.4

AIN0.5

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1100

AIN0.0

AIN0.1

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1101

+(AIN0.0)

-(AIN0.1)

AIN0.2

AIN0.3

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1110

AIN0.0

AIN0.1

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

1111

+(AIN0.0)

-(AIN0.1)

+(AIN0.2)

-(AIN0.3)

+(AIN0.4)

-(AIN0.5)

+(AIN0.6)

-(AIN0.7)

TEMP

SENSOR

DS008-1.1-JUN03

Page 75

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.8. ADC0CN: ADC0 Control Register

Bit7:

AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.

Bit6:

AD0TM: ADC Track Mode Bit.
0: When the ADC is enabled, tracking is continuous unless a conversion is in process.
1: Tracking Defined by ADCM1-0 bits.

Bit5:

Bit4:

Bits3-2:

Bit1:

Bit0:

AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.

SFR Page:
SFR Address:

0
0xE8

(bit addressable)

R/W

Reset Value

AD0EN

AD0TM

AD0INT AD0BUSY AD0CM1

AD0CM0

AD0WINT

AD0LJST 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 77

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.11. ADC0 Data Word Example

10-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows:
ADC0H[1:0]:ADC0L[7:0], if AD0LJST = 0

(ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise =
000000b).

ADC0H[7:0]:ADC0L[7:6], if AD0LJST = 1

(ADC0L[5:0] = 00b).

Example: ADC0 Data Word Conversion Map, AIN0.0 Input in Single-Ended Mode

(AMX0CF = 0x00, AMX0SL = 0x00)

Example: ADC0 Data Word Conversion Map, AIN0.0-AIN0.1 Differential Input Pair

(AMX0CF = 0x01, AMX0SL = 0x00)

For AD0LJST = 0:

; `n' = 10 for Single-Ended; `n'= 9 for Differential.

AIN0.0-AGND

(Volts)

ADC0H:ADC0L

(AD0LJST = 0)

ADC0H:ADC0L

(AD0LJST = 1)

VREF * (1023/1024)

0x03FF

0xFFC0

VREF / 2

0x0800

0x8000

VREF * (511/1024)

0x01FF

0x7FC0

0x0000

AIN0.0-AIN0.1

(Volts)

ADC0H:ADC0L

(AD0LJST = 0)

ADC0H:ADC0L

(AD0LJST = 1)

VREF * (511/512)

0x01FF

0x7FC0

VREF / 2

0x0100

0x4000

VREF * (1/512)

0x0001

0x0040

0x0000

-VREF * (1/512)

0xFFFF (-1d)

0xFFC0

-VREF / 2

0xFF00 (-256d)

0xC000

-VREF

0xFE00 (-512d)

0x8000

Code

Vin

Gain

VREF

---------------

Page 78

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

6.3.

ADC0 Programmable Window Detector

The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits,
and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven
system, saving code space and CPU bandwidth while delivering faster system response times. The window detector
interrupt flag (AD0WINT in ADC0CN) can also be used in polled mode. The high and low bytes of the reference
words are loaded into the ADC0 Greater-Than and ADC0 Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH,
and ADC0LTL). Reference comparisons are shown starting on page 80. Notice that the window detector flag can be
asserted when the measured data is inside or outside the user-programmed limits, depending on the programming of
the ADC0GTx and ADC0LTx registers.

Figure 6.12. ADC0GTH: ADC0 Greater-Than Data High Byte Register

Bits7-0:

High byte of ADC0 Greater-Than Data Word.

SFR Page:
SFR Address:

0
0xC5

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Figure 6.13. ADC0GTL: ADC0 Greater-Than Data Low Byte Register

Bits7-0:

Low byte of ADC0 Greater-Than Data Word.

SFR Page:
SFR Address:

0
0xC4

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Page 80

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data

0x03FF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

ADWINT=1

ADWINT
notaffected

ADC Data

Word

0x03FF

0x0201

0x0200

0x01FF

0x0101

0x0100

0x00FF

0x0000

ADWINT=1

ADWINT
notaffected

ADWINT=1

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC0GTH:ADC0GTL

ADC0LTH:ADC0LTL

InputVoltage

(AD0.0 - AGND)

REF x (1023/1024)

REF x (256/1024)

REF x (512/1024)

InputVoltage

(AD0.0 - AGND)

REF x (1023/1024)

REF x (256/1024)

REF x (512/1024)

DS008-1.1-JUN03

Page 81

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0x01FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xFE00

ADWINT=1

ADWINT
notaffected

0x01FF

0x0101

0x0100

0x00FF

0x0000

0xFFFF

0xFFFE

0xFE00

ADWINT=1

ADWINT
notaffected

-REF

InputVoltage

(AD0.0 - AD0.1)

ADWINT=1

REF x (511/512)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (256/512)

REF x (-1/512)

-REF

InputVoltage

(AD0.0 - AD0.1)

REF x (511/512)

REF x (256/512)

REF x (-1/512)

Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data

Page 82

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0xFFC0

0x8040

0x8000

0x7FC0

0x4040

0x4000

0x3FC0

0x0000

ADWINT=1

ADWINT
notaffected

ADC Data

Word

0xFFC0

0x8040

0x8000

0x7FC0

0x4040

0x4000

0x3FC0

0x0000

ADWINT=1

ADWINT
notaffected

ADWINT=1

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC0GTH:ADC0GTL

ADC0LTH:ADC0LTL

InputVoltage

(AD0.0 - AGND)

REF x (1023/1024)

REF x (256/1024)

REF x (512/1024)

InputVoltage

(AD0.0 - AGND)

REF x (1023/1024)

REF x (256/1024)

REF x (512/1024)

Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data

DS008-1.1-JUN03

Page 83

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0x7FC0

0x2040

0x2000

0x1FC0

0x0000

0xFFC0

0xFF80

0x8000

ADWINT=1

ADWINT
notaffected

0x7FC0

0x2040

0x2000

0x1FC0

0x0000

0xFFC0

0xFF80

0x8000

ADWINT=1

ADWINT
notaffected

-REF

InputVoltage

(AD0.0 - AD0.1)

ADWINT=1

REF x (511/512)

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

ADC Data

Word

ADC Data

Word

ADC0LTH:ADC0LTL

ADC0GTH:ADC0GTL

REF x (128/512)

REF x (-1/512)

-REF

InputVoltage

(AD0.0 - AD0.1)

REF x (511/512)

REF x (128/512)

REF x (-1/512)

Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `1',
ADC0LTH:ADC0LTL = 0x2000,
ADC0GTH:ADC0GTL = 0xFFC0.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0x2000 and
> 0xFFC0. (Two's-complement math.)

Given:
AMX0SL = 0x00, AMX0CF = 0x01,
AD0LJST = `1',
ADC0LTH:ADC0LTL = 0xFFC0,
ADC0GTH:ADC0GTL = 0x2000.
An ADC0 End of Conversion will cause an ADC0
Window Compare Interrupt (AD0WINT = `1') if
the resulting ADC0 Data Word is < 0xFFC0 or
> 0x2000. (Two's-complement math.)

Page 84

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F122/3/6/7)

VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution

bits

Integral Nonlinearity

±1

LSB

Differential Nonlinearity

Guaranteed Monotonic

±1

LSB

Offset Error

±0.5

LSB

Full Scale Error

Differential mode

-1.5±0.5

LSB

Offset Temperature Coefficient

±0.25

ppm/°C

DYNAMIC PERFORMANCE (10 kHz sine-wave input, 0 to 1 dB below Full Scale, 100 ksps

Signal-to-Noise Plus Distortion

Total Harmonic Distortion

Up to the 5

harmonic

-70

Spurious-Free Dynamic Range

CONVERSION RATE

SAR Clock Frequency

2.5

MHz

Conversion Time in SAR Clocks

clocks

Track/Hold Acquisition Time

1.5

µs

Throughput Rate

100

ksps

ANALOG INPUTS

Input Voltage Range

Single-ended operation

VREF

*Common-mode Voltage Range

Differential operation

AGND

AV+

Input Capacitance

TEMPERATURE SENSOR

Linearity

Note 1

±0.2

°C

Gain

Note 2

2.86

±0.034

mV / °C

Offset

Note 1, Note 2, (Temp = 0 °C)

776

±8.5

POWER SPECIFICATIONS

Power Supply Current (AV+ sup-
plied to ADC)

Operating Mode, 100 ksps

450

900

µA

Power Supply Rejection

±0.3

mV/V

Note 1: Includes ADC offset, gain, and linearity variations.
Note 2: Represents one standard deviation from the mean.

DS008-1.1-JUN03

Page 85

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

ADC2 (8-BIT ADC)

The ADC2 subsystem for the C8051F120/1/2/3/4/5/6/7 consists of an 8-channel, configurable analog multiplexer
(AMUX2), a programmable gain amplifier (PGA2), and a 500 ksps, 8-bit successive-approximation-register ADC
with integrated track-and-hold (see block diagram in Figure 7.1). The AMUX2, PGA2, and Data Conversion Modes
are all configurable under software control via the Special Function Registers shown in Figure 7.1. The ADC2 sub-
system (8-bit ADC, track-and-hold and PGA) is enabled only when the AD2EN bit in the ADC2 Control register
(ADC2CN) is set to logic 1. The ADC2 subsystem is in low power shutdown when this bit is logic 0. The voltage ref-
erence used by ADC2 is selected as described in

Section "9. VOLTAGE REFERENCE (C8051F120/2/4/6)" on

page 107

for C8051F120/2/4/6 devices, or

Section "10. VOLTAGE REFERENCE (C8051F121/3/5/7)" on

page 109

for C8051F121/3/5/7 devices.

7.1.

Analog Multiplexer and PGA

Eight ADC2 channels are available for measurement, as selected by the AMX2SL register (see Figure 7.5). The PGA
amplifies the ADC2 output signal by an amount determined by the states of the AMP2GN2-0 bits in the ADC2 Con-
figuration register, ADC2CF (Figure 7.6). The PGA can be software-programmed for gains of 0.5, 1, 2, or 4. Gain
defaults to 0.5 on reset.

Important Note: AIN2 pins also function as Port 1 I/O pins, and must be configured as analog inputs when used as
ADC2 inputs. To configure an AIN2 pin for analog input, set to `0' the corresponding bit in register P1MDIN. Port 1
pins selected as analog inputs are skipped by the Digital I/O Crossbar. See

Section "19.1.5. Configuring Port 1 Pins

as Analog Inputs" on page 219

for more information on configuring the AIN2 pins.

Figure 7.1. ADC2 Functional Block Diagram

8-Bit
SAR

ADC

+
-

AV+

AD2EN

SYSC

AGND

ADC2CF

AMX2SL

ADC2CN

AD2W

INT

AD2BUS

I
N

Start Conversion

Timer 3 Overflow

Timer 2 Overflow

000

001

010

011

Write to AD2BUSY

CNVSTR2

1xx

Write to AD0BUSY
(synchronized with
ADC0)

AD0

AD1

AD2

8-to-1

AMUX

AIN2.0 (P1.0)

AIN2.1 (P1.1)

AIN2.2 (P1.2)

AIN2.3 (P1.3)

AIN2.4 (P1.4)

AIN2.5 (P1.5)

AIN2.6 (P1.6)

AIN2.7 (P1.7)

AMX2CF

01I

23I

45I

67I

ADC2LTH

ADC2GTH

Dig

Comp

AD2WINT

2CM

Page 86

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

7.2.

ADC2 Modes of Operation

ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock) is a divided version
of the system clock, determined by the AD2SC bits in the ADC2CF register. The maximum ADC2 conversion clock
is 7.5 MHz.

7.2.1.

Starting a Conversion

A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start of Conver-
sion Mode bits (AD2CM2-0) in ADC2CN. Conversions may be initiated by:

Writing a `1' to the AD2BUSY bit of ADC2CN;

A Timer 3 overflow (i.e. timed continuous conversions);

A rising edge detected on the external ADC convert start signal, CNVSTR2;

A Timer 2 overflow (i.e. timed continuous conversions);

Writing a `1' to the AD0BUSY of register ADC0CN (initiate conversion of ADC2 and ADC0 with a

single software command).

During conversion, the AD2BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The falling
edge of AD2BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC2CN. Converted data is
available in the ADC2 data word, ADC2.

When a conversion is initiated by writing a `1' to AD2BUSY, it is recommended to poll AD2INT to determine when
the conversion is complete. The recommended procedure is:

Step 1. Write a `0' to AD2INT;
Step 2. Write a `1' to AD2BUSY;
Step 3. Poll AD2INT for `1';
Step 4. Process ADC2 data.

When CNVSTR2 is used as a conversion start source, it must be enabled in the crossbar, and the corresponding pin
must be set to open-drain, high-impedance mode (see

Section "19. PORT INPUT/OUTPUT" on page 215

for more

details on Port I/O configuration).

7.2.2.

Tracking Modes

The AD2TM bit in register ADC2CN controls the ADC2 track-and-hold mode. In its default state, the ADC2 input is
continuously tracked, except when a conversion is in progress. When the AD2TM bit is logic 1, ADC2 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks
(after the start-of-conversion signal). When the CNVSTR2 signal is used to initiate conversions in low-power track-
ing mode, ADC2 tracks only when CNVSTR2 is low; conversion begins on the rising edge of CNVSTR2 (see
Figure 7.2). Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Low-power Track-and-Hold mode is also useful when AMUX or PGA settings are frequently changed, due to the set-
tling time requirements described in

Section "7.2.3. Settling Time Requirements" on page 88

Page 88

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

7.2.3.

Settling Time Requirements

When the ADC2 input configuration is changed (i.e., a different MUX or PGA selection), a minimum tracking time is
required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resis-
tance, the ADC2 sampling capacitance, any external source resistance, and the accuracy required for the conversion.
Figure 7.3 shows the equivalent ADC2 input circuit. The required ADC2 settling time for a given settling accuracy
(SA) may be approximated by Equation 7.1. Note: An absolute minimum settling time of 800 ns required after any
MUX selection. Note that in low-power tracking mode, three SAR2 clocks are used for tracking at the start of every
conversion. For most applications, these three SAR2 clocks will meet the tracking requirements.

Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R

TOTAL

is the sum of the ADC2 MUX resistance and any external source resistance.

n is the ADC resolution in bits (8).

Equation 7.1. ADC2 Settling Time Requirements

-------

TOTAL

SAMPLE

MUX

= 5k

Input

= R

MUX

* C

SAMPLE

MUX

= 5k

SAMPLE

= 5pF

SAMPLE

= 5pF

MUX Select

Differential Mode

AIN2.x

AIN2.y

MUX

= 5k

SAMPLE

= 5pF

Input

= R

MUX

* C

SAMPLE

MUX Select

Single-Ended Mode

AIN2.x

Note: When the PGA gain is set to 0.5, C

SAMPLE

= 3pF

Figure 7.3. ADC2 Equivalent Input Circuit

DS008-1.1-JUN03

Page 89

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 7.4. AMX2CF: AMUX2 Configuration Register

Bits7-4:

UNUSED. Read = 0000b; Write = don't care.

Bit3:

PIN67IC: AIN2.6, AIN2.7 Input Pair Configuration Bit.
0: AIN2.6 and AIN2.7 are independent single-ended inputs.
1: AIN2.6 and AIN2.7 are (respectively) +, - differential input pair.

Bit2:

PIN45IC: AIN2.4, AIN2.5 Input Pair Configuration Bit.
0: AIN2.4 and AIN2.5 are independent single-ended inputs.
1: AIN2.4 and AIN2.5 are (respectively) +, - differential input pair.

Bit1:

PIN23IC: AIN2.2, AIN2.3 Input Pair Configuration Bit.
0: AIN2.2 and AIN2.3 are independent single-ended inputs.
1: AIN2.2 and AIN2.3 are (respectively) +, - differential input pair.

Bit0:

PIN01IC: AIN2.0, AIN2.1 Input Pair Configuration Bit.
0: AIN2.0 and AIN2.1 are independent single-ended inputs.
1: AIN2.0 and AIN2.1 are (respectively) +, - differential input pair.

NOTE:

The ADC2 Data Word is in 2's complement format for channels configured as differential.

SFR Page:
SFR Address:

2
0xBA

R/W

Reset Value

PIN67IC

PIN45IC

PIN23IC

PIN01IC

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Page 90

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 7.5. AMX2SL: AMUX2 Channel Select Register

Bits7-3:

UNUSED. Read = 00000b; Write = don't care.

Bits2-0:

AMX2AD2-0: AMX2 Address Bits.
000-111b: ADC Inputs selected per chart below.

SFR Page:
SFR Address:

2
0xBB

R/W

Reset Value

AMX2AD2 AMX2AD1 AMX2AD0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AMX2AD2-0

000

001

010

011

100

101

110

111

i
t
s

-
0

0000

AIN2.0

AIN2.1

AIN2.2

AIN2.3

AIN2.4

AIN2.5

AIN2.6

AIN2.7

0001

+(AIN2.0)

-(AIN2.1)

AIN2.2

AIN2.3

AIN2.4

AIN2.5

AIN2.6

AIN2.7

0010

AIN2.0

AIN2.1

+(AIN2.2)

-(AIN2.3)

AIN2.4

AIN2.5

AIN2.6

AIN2.7

0011

+(AIN2.0)

-(AIN2.1)

+(AIN2.2)

-(AIN2.3)

AIN2.4

AIN2.5

AIN2.6

AIN2.7

0100

AIN2.0

AIN2.1

AIN2.2

AIN2.3

+(AIN2.4)

-(AIN2.5)

AIN2.6

AIN2.7

0101

+(AIN2.0)

-(AIN2.1)

AIN2.2

AIN2.3

+(AIN2.4)

-(AIN2.5)

AIN2.6

AIN2.7

0110

AIN2.0

AIN2.1

+(AIN2.2)

-(AIN2.3)

+(AIN2.4)

-(AIN2.5)

AIN2.6

AIN2.7

0111

+(AIN2.0)

-(AIN2.1)

+(AIN2.2)

-(AIN2.3)

+(AIN2.4)

-(AIN2.5)

AIN2.6

AIN2.7

1000

AIN2.0

AIN2.1

AIN2.2

AIN2.3

AIN2.4

AIN2.5

+(AIN2.6)

-(AIN2.7)

1001

+(AIN2.0)

-(AIN2.1)

AIN2.2

AIN2.3

AIN2.4

AIN2.5

+(AIN2.6)

-(AIN2.7)

1010

AIN2.0

AIN2.1

+(AIN2.2)

-(AIN2.3)

AIN2.4

AIN2.5

+(AIN2.6)

-(AIN2.7)

1011

+(AIN2.0)

-(AIN2.1)

+(AIN2.2)

-(AIN2.3)

AIN2.4

AIN2.5

+(AIN2.6)

-(AIN2.7)

1100

AIN2.0

AIN2.1

AIN2.2

AIN2.3

+(AIN2.4)

-(AIN2.5)

+(AIN2.6)

-(AIN2.7)

1101

+(AIN2.0)

-(AIN2.1)

AIN2.2

AIN2.3

+(AIN2.4)

-(AIN2.5)

+(AIN2.6)

-(AIN2.7)

1110

AIN2.0

AIN2.1

+(AIN2.2)

-(AIN2.3)

+(AIN2.4)

-(AIN2.5)

+(AIN2.6)

-(AIN2.7)

1111

+(AIN2.0)

-(AIN2.1)

+(AIN2.2)

-(AIN2.3)

+(AIN2.4)

-(AIN2.5)

+(AIN2.6)

-(AIN2.7)

Page 92

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 7.7. ADC2CN: ADC2 Control Register

Bit7:

AD2EN: ADC2 Enable Bit.
0: ADC2 Disabled. ADC2 is in low-power shutdown.
1: ADC2 Enabled. ADC2 is active and ready for data conversions.

Bit6:

AD2TM: ADC2 Track Mode Bit.
0: Normal Track Mode: When ADC2 is enabled, tracking is continuous unless a conversion is in pro-
cess.
1: Low-power Track Mode: Tracking Defined by AD2CM2-0 bits (see below).

Bit5:

AD2INT: ADC2 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC2 has not completed a data conversion since the last time this flag was cleared.
1: ADC2 has completed a data conversion.

Bit4:

AD2BUSY: ADC2 Busy Bit.
Read:
0: ADC2 Conversion is complete or a conversion is not currently in progress. AD2INT is set to
logic 1 on the falling edge of AD2BUSY.
1: ADC2 Conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC2 Conversion if AD2CM2-0 = 000b

Bits3-1:

AD2CM2-0: ADC2 Start of Conversion Mode Select.
AD2TM = 0:
000: ADC2 conversion initiated on every write of `1' to AD2BUSY.
001: ADC2 conversion initiated on overflow of Timer 3.
010: ADC2 conversion initiated on rising edge of external CNVSTR2.
011: ADC2 conversion initiated on overflow of Timer 2.
1xx: ADC2 conversion initiated on write of `1' to AD0BUSY (synchronized with ADC0 software-
commanded conversions).
AD2TM = 1:
000: Tracking initiated on write of `1' to AD2BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.
001: Tracking initiated on overflow of Timer 3 and lasts 3 SAR2 clocks, followed by conversion.
010: ADC2 tracks only when CNVSTR2 input is logic low; conversion starts on rising CNVSTR2
edge.
011: Tracking initiated on overflow of Timer 2 and lasts 3 SAR2 clocks, followed by conversion.
1xx: Tracking initiated on write of `1' to AD0BUSY and lasts 3 SAR2 clocks, followed by conver-
sion.

Bit0:

AD2WINT: ADC2 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC2 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC2 Window Comparison Data match has occurred.

SFR Page:
SFR Address:

2
0xE8

(bit addressable)

R/W

Reset Value

AD2EN

AD2TM

AD2INT AD2BUSY AD2CM2 AD2CM1

AD2CM0

AD2WINT 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 93

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 7.8. ADC2: ADC2 Data Word Register

Bits7-0:

ADC2 Data Word.

SFR Page:
SFR Address:

2
0xBE

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Figure 7.9. ADC2 Data Word Example

Single-Ended Example:
8-bit ADC Data Word appears in the ADC2 Data Word Register as follows:
Example: ADC2 Data Word Conversion Map, Single-Ended AIN2.0 Input

(AMX2CF = 0x00; AMX2SL = 0x00)

Differential Example:
8-bit ADC Data Word appears in the ADC2 Data Word Register as follows:
Example: ADC2 Data Word Conversion Map, Differential AIN2.0-AIN2.1 Input

(AMX2CF = 0x01; AMX2SL = 0x00)

AIN2.0-AGND

(Volts)

ADC2

VREF * (255/256)

0xFF

VREF * (128/256)

0x80

VREF * (64/256)

0x40

0x00

AIN2.0-AIN2.1

(Volts)

ADC2

VREF * (127/128)

0x7F

VREF * (64/128)

0x40

0x00

-VREF * (64/128)

0xC0 (-64d)

-VREF * (128/128)

0x80 (-128d)

Code

Vin

Gain

VREF

---------------

256

Code

Vin

Gain

× REF

-------------------------

256

Page 94

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

7.3.

ADC2 Programmable Window Detector

The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed limits,
and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system,
saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt
flag (AD2WINT in register ADC2CN) can also be used in polled mode. The ADC2 Greater-Than (ADC2GT) and
Less-Than (ADC2LT) registers hold the comparison values. Example comparisons for Differential and Single-ended
modes are shown in Figure 7.11 and Figure 7.10, respectively. Notice that the window detector flag can be pro-
grammed to indicate when measured data is inside or outside of the user-programmed limits, depending on the con-
tents of the ADC2LT and ADC2GT registers.

7.3.1.

Window Detector In Single-Ended Mode

Figure 7.10 shows two example window comparisons for Single-ended mode, with ADC2LT = 0x20 and
ADC2GT = 0x10. Notice that in Single-ended mode, the codes vary from 0 to VREF*(255/256) and are represented
as 8-bit unsigned integers. In the left example, an AD2WINT interrupt will be generated if the ADC2 conversion
word (ADC2) is within the range defined by ADC2GT and ADC2LT (if 0x10

< ADC2 < 0x20). In the right example,

and AD2WINT interrupt will be generated if ADC2 is outside of the range defined by ADC2GT and ADC2LT
(if ADC2

< 0x10 or ADC2 > 0x20).

Figure 7.10. ADC2 Window Compare Examples, Single-Ended Mode

0xFF

0x21

0x20

0x1F

0x11

0x10

0x0F

0x00

InputVoltage

(AIN2.x - AGND)

REF x (255/256)

REF x (32/256)

REF x (16/256)

AD2WINT=1

AD2WINT

notaffected

AD2WINT

notaffected

ADC2LT

ADC2GT

0xFF

0x21

0x20

0x1F

0x11

0x10

0x0F

0x00

InputVoltage

(AIN2.x - AGND)

REF x (255/256)

REF x (32/256)

REF x (16/256)

AD2WINT

notaffected

ADC2GT

ADC2LT

AD2WINT=1

ADC2

DS008-1.1-JUN03

Page 95

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

7.3.2.

Window Detector In Differential Mode

Figure 7.11 shows two example window comparisons for differential mode, with ADC2LT = 0x10 (+16d) and
ADC2GT = 0xFF (-1d). Notice that in Differential mode, the codes vary from -VREF to VREF*(127/128) and are
represented as 8-bit 2's complement signed integers. In the left example, an AD2WINT interrupt will be generated if
the ADC2 conversion word (ADC2L) is within the range defined by ADC2GT and ADC2LT (if 0xFF (-1d) < ADC2
< 0x0F (16d)). In the right example, an AD2WINT interrupt will be generated if ADC2 is outside of the range
defined by ADC2GT and ADC2LT (if ADC2 < 0xFF (-1d) or ADC2 > 0x10 (+16d)).

Figure 7.11. ADC2 Window Compare Examples, Differential Mode

0x7F (127d)

0x11 (17d)

0x10 (16d)

0x0F (15d)

0x00 (0d)

0xFF (-1d)

0xFE (-2d)

0x80 (-128d)

-REF

InputVoltage

(AIN2.x - AIN2.y)

REF x (127/128)

REF x (16/128)

REF x (-1/256)

0x7F (127d)

0x11 (17d)

0x10 (16d)

0x0F (15d)

0x00 (0d)

0xFF (-1d)

0xFE (-2d)

0x80 (-128d)

-REF

InputVoltage

(AIN2.x - AIN2.y)

REF x (127/128)

REF x (16/128)

REF x (-1/256)

AD2WINT=1

AD2WINT

notaffected

AD2WINT

notaffected

ADC2LT

ADC2GT

AD2WINT

notaffected

ADC2GT

ADC2LT

AD2WINT=1

ADC2

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 7.1. ADC2 Electrical Characteristics

VDD = 3.0 V, AV+ = 3.0 V, VREF2 = 2.40 V (REFBE=0), PGA gain = 1, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution

bits

Integral Nonlinearity

±1

LSB

Differential Nonlinearity

Guaranteed Monotonic

±1

LSB

Offset Error

0.5±0.3

LSB

Full Scale Error

Differential mode

-1±0.2

LSB

Offset Temperature Coefficient

TBD

ppm/°C

DYNAMIC PERFORMANCE (10 kHz sine-wave input, 1 dB below Full Scale, 500 ksps

Signal-to-Noise Plus Distortion

TBD

Total Harmonic Distortion

Up to the 5

harmonic

Spurious-Free Dynamic Range

CONVERSION RATE

SAR Clock Frequency

7.5

MHz

Conversion Time in SAR Clocks

clocks

Track/Hold Acquisition Time

800

Throughput Rate

500

ksps

ANALOG INPUTS

Input Voltage Range

VREF

Input Capacitance

POWER SPECIFICATIONS

Power Supply Current (AV+ sup-
plied to ADC2)

Operating Mode, 500 ksps

420

TBD

µA

Power Supply Rejection

±0.3

mV/V

DS008-1.1-JUN03

Page 99

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

DACS, 12-BIT VOLTAGE MODE

Each C8051F12x device includes two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each
DAC has an output swing of 0 V to (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The
DACs may be enabled/disabled via their corresponding control registers, DAC0CN and DAC1CN. While disabled,
the DAC output is maintained in a high-impedance state, and the DAC supply current falls to 1 µA or less. The volt-
age reference for each DAC is supplied at the VREFD pin (C8051F120/2/4/6 devices) or the VREF pin (C8051F121/
3/5/7 devices). Note that the VREF pin on C8051F121/3/5/7 devices may be driven by the internal voltage reference
or an external source. If the internal voltage reference is used it must be enabled in order for the DAC outputs to be
valid. See

Section "9. VOLTAGE REFERENCE (C8051F120/2/4/6)" on page 107

Section "10. VOLTAGE

REFERENCE (C8051F121/3/5/7)" on page 109

for more information on configuring the voltage reference for the

DACs.

8.1.

DAC Output Scheduling

Each DAC features a flexible output update mechanism which allows for seamless full-scale changes and supports
jitter-free updates for waveform generation. The following examples are written in terms of DAC0, but DAC1 opera-
tion is identical.

8.1.1.

Update Output On-Demand

In its default mode (DAC0CN.[4:3] = `00') the DAC0 output is updated "on-demand" on a write to the high-byte of
the DAC0 data register (DAC0H). It is important to note that writes to DAC0L are held, and have no effect on the
DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data registers, the 12-bit
data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into DAC0 after

DAC0

AV+

AGND

REF

DAC0

DAC

DAC0EN

DAC0MD1
DAC0MD0

DAC0DF2
DAC0DF1
DAC0DF0

DAC

MUX

Latch

Latc

DAC1

AV+

AGND

REF

DAC1

DAC1CN

DAC1EN

DAC1MD1
DAC1MD0

DAC1DF2
DAC1DF1
DAC1DF0

DAC1H

DAC1L

MUX

Latch

Latc

mer

DAC1H

mer

Figure 8.1. DAC Functional Block Diagram

Page 100

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the
full 12-bit resolution is required. The DAC can be used in 8-bit mode by initializing DAC0L to the desired value (typ-
ically 0x00), and writing data to only DAC0H (also see

Section 8.2

for information on formatting the 12-bit DAC

data word within the 16-bit SFR space).

8.1.2.

Update Output Based on Timer Overflow

Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow independently of the
processor, the DAC outputs can use a Timer overflow to schedule an output update event. This feature is useful in
systems where the DAC is used to generate a waveform of a defined sampling rate by eliminating the effects of vari-
able interrupt latency and instruction execution on the timing of the DAC output. When the DAC0MD bits
(DAC0CN.[4:3]) are set to `01', `10', or `11', writes to both DAC data registers (DAC0L and DAC0H) are held until
an associated Timer overflow event (Timer 3, Timer 4, or Timer 2, respectively) occurs, at which time the
DAC0H:DAC0L contents are copied to the DAC input latches allowing the DAC output to change to the new value.

8.2.

DAC Output Scaling/Justification

In some instances, input data should be shifted prior to a DAC0 write operation to properly justify data within the
DAC input registers. This action would typically require one or more load and shift operations, adding software over-
head and slowing DAC throughput. To alleviate this problem, the data-formatting feature provides a means for the
user to program the orientation of the DAC0 data word within data registers DAC0H and DAC0L. The three
DAC0DF bits (DAC0CN.[2:0]) allow the user to specify one of five data word orientations as shown in the DAC0CN
register definition.

DAC1 is functionally the same as DAC0 described above. The electrical specifications for both DAC0 and DAC1 are
given in Table 8.1.

Page 102

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 8.4. DAC0CN: DAC0 Control Register

Bit7:

DAC0EN: DAC0 Enable Bit.
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode.
1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational.

Bits6-5:

UNUSED. Read = 00b; Write = don't care.

Bits4-3:

DAC0MD1-0: DAC0 Mode Bits.
00: DAC output updates occur on a write to DAC0H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.

Bits2-0:

DAC0DF2-0: DAC0 Data Format Bits:

000:

The most significant nibble of the DAC0 Data Word is in DAC0H[3:0], while the least
significant byte is in DAC0L.

001:

The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least
significant 7-bits are in DAC0L[7:1].

010:

The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least
significant 6-bits are in DAC0L[7:2].

011:

The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least
significant 5-bits are in DAC0L[7:3].

1xx:

The most significant 8-bits of the DAC0 Data Word is in DAC0H[7:0], while the least
significant 4-bits are in DAC0L[7:4].

R/W

Reset Value

DAC0EN

DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xD4
0

DAC0H

DAC0L

MSB

LSB

DAC0H

DAC0L

MSB

LSB

DAC0H

DAC0L

MSB

LSB

DAC0H

DAC0L

MSB

LSB

DAC0H

DAC0L

MSB

LSB

Page 104

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 8.7. DAC1CN: DAC1 Control Register

Bit7:

DAC1EN: DAC1 Enable Bit.
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode.
1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational.

Bits6-5:

UNUSED. Read = 00b; Write = don't care.

Bits4-3:

DAC1MD1-0: DAC1 Mode Bits:
00: DAC output updates occur on a write to DAC1H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.

Bits2-0:

DAC1DF2: DAC1 Data Format Bits:

000:

The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.

001:

The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits are in DAC1L[7:1].

010:

The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits are in DAC1L[7:2].

011:

The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits are in DAC1L[7:3].

1xx:

The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least
significant 4-bits are in DAC1L[7:4].

R/W

Reset Value

DAC1EN

DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xD4
1

DAC1H

DAC1L

MSB

LSB

DAC1H

DAC1L

MSB

LSB

DAC1H

DAC1L

MSB

LSB

DAC1H

DAC1L

MSB

LSB

DAC1H

DAC1L

MSB

LSB

DS008-1.1-JUN03

Page 105

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 8.1. DAC Electrical Characteristics

VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution

bits

Integral Nonlinearity

±1.5

LSB

Differential Nonlinearity

±1

LSB

Output Noise

No Output Filter
100 kHz Output Filter
10 kHz Output Filter

250
128

µVrms

Offset Error

Data Word = 0x014

±3

±30

Offset Tempco

ppm/°C

Gain Error

±20

±60

Gain-Error Tempco

ppm/°C

VDD Power Supply Rejection
Ratio

-60

Output Impedance in Shutdown
Mode

DACnEN = 0

100

Output Sink Current

300

µA

Output Short-Circuit Current

Data Word = 0xFFF

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Load = 40pF

0.44

V/µs

Output Settling Time to 1/2 LSB

Load = 40pF, Output swing from code
0xFFF to 0x014

µs

Output Voltage Swing

VREF-

1LSB

Startup Time

µs

ANALOG OUTPUTS

Load Regulation

= 0.01mA to 0.3mA at code 0xFFF

ppm

POWER CONSUMPTION (each DAC)

Power Supply Current (AV+ sup-
plied to DAC)

Data Word = 0x7FF

110

400

µA

DS008-1.1-JUN03

Page 107

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

VOLTAGE REFERENCE (C8051F120/2/4/6)

The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference
input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage refer-
ence output. ADC0 may also reference the DAC0 output internally, and ADC2 may reference the analog power sup-
ply voltage, via the VREF multiplexers shown in Figure 9.1.

The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator
and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system
components or to the voltage reference input pins shown in Figure 9.1. The maximum load seen by the VREF pin
must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to
AGND, as shown in Figure 9.1.

The Reference Control Register, REF0CN (defined in Figure 9.2) enables/disables the internal reference generator
and selects the reference inputs for ADC0 and ADC2. The BIASE bit in REF0CN enables the on-board reference
generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,
the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the
buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,
BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0.
Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage refer-
ence is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are
being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD2VRS select the ADC0
and ADC2 voltage reference sources, respectively. The electrical specifications for the Voltage Reference are given in
Table 9.1.

Recommended Bypass

Capacitors

VREF

DAC0

DAC1

Ref

VREFD

AV+

ADC2

ADC0

VREF2

Ref

VREF0

4.7

µF

0.1

µF

External

Voltage

Reference

Circuit

VDD

DGND

REF0CN

ASE

REFBE

BIASE

Bias to

ADCs,

DACs

1.2V

Band-Gap

Figure 9.1. Voltage Reference Functional Block Diagram

Page 108

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see

Section "5.1. Analog

Multiplexer and PGA" on page 49

for C8051F120/1/4/5 devices, or

Section "6.1. Analog Multiplexer and PGA"

on page 67

for C8051F122/3/6/7 devices). The TEMPE bit within REF0CN enables and disables the temperature

sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements per-
formed on the sensor while disabled result in undefined data.

Table 9.1. Voltage Reference Electrical Characteristics

VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INTERNAL REFERENCE (REFBE = 1)

Output Voltage

25°C ambient

2.36

2.43

2.48

VREF Short-Circuit Current

VREF Temperature Coefficient

ppm/°C

Load Regulation

Load = 0 to 200 µA to AGND

0.5

ppm/µA

VREF Turn-on Time 1

4.7µF tantalum, 0.1µF ceramic bypass

VREF Turn-on Time 2

0.1µF ceramic bypass

µs

VREF Turn-on Time 3

no bypass cap

µs

EXTERNAL REFERENCE (REFBE = 0)

Input Voltage Range

1.00

(AV+) -

0.3

Input Current

µA

Figure 9.2. REF0CN: Reference Control Register

Bits7-5:

UNUSED. Read = 000b; Write = don't care.

Bit4:

AD0VRS: ADC0 Voltage Reference Select.
0: ADC0 voltage reference from VREF0 pin.
1: ADC0 voltage reference from DAC0 output.

Bit3:

AD2VRS: ADC2 Voltage Reference Select.
0: ADC2 voltage reference from VREF2 pin.
1: ADC2 voltage reference from AV+.

Bit2:

TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.

Bit1:

BIASE: ADC/DAC Bias Generator Enable Bit. (Must be `1' if using ADC or DAC).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.

Bit0:

REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.

SFR Page:
SFR Address:

0
0xD1

R/W

Reset Value

AD0VRS

AD2VRS

TEMPE

BIASE

REFBE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 109

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

10.

VOLTAGE REFERENCE (C8051F121/3/5/7)

The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator
and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system
components or to the VREFA input pin shown in Figure 10.1. The maximum load seen by the VREF pin must be less
than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to AGND, as
shown in Figure 10.1.

The VREFA pin provides a voltage reference input for ADC0 and ADC2. ADC0 may also reference the DAC0 out-
put internally, and ADC2 may reference the analog power supply voltage, via the VREF multiplexers shown in
Figure 10.1.

The Reference Control Register, REF0CN (defined in Figure 10.2) enables/disables the internal reference generator
and selects the reference inputs for ADC0 and ADC2. The BIASE bit in REF0CN enables the on-board reference
generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,
the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the
buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,
BIASE and REFBE must both be set to 1 (this includes any time a DAC is used). If the internal reference is not used,
REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either ADC is used, regardless of
whether the voltage reference is derived from the on-chip reference or supplied by an off-chip source. If neither the
ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and
AD2VRS select the ADC0 and ADC2 voltage reference sources, respectively. The electrical specifications for the
Voltage Reference are given in Table 10.1.

Recommended Bypass

Capacitors

VREF

DAC0

DAC1

Ref

AV+

ADC2

ADC0

Ref

VREFA

4.7

µF

0.1

µF

External

Voltage

Reference

Circuit

VDD

DGND

REF0CN

REFBE

BIASE

Bias to

ADCs,

DACs

1.2V

Band-Gap

Figure 10.1. Voltage Reference Functional Block Diagram

Page 110

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see

Section "5.1. Analog

Multiplexer and PGA" on page 49

for C8051F120/1/4/5 devices, or

Section "6.1. Analog Multiplexer and PGA"

on page 67

for C8051F122/3/6/7 devices). The TEMPE bit within REF0CN enables and disables the temperature

sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements per-
formed on the sensor while disabled result in undefined data.

Table 10.1. Voltage Reference Electrical Characteristics

VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INTERNAL REFERENCE (REFBE = 1)

Output Voltage

25°C ambient

2.36

2.43

2.48

VREF Short-Circuit Current

VREF Temperature Coefficient

ppm/°C

Load Regulation

Load = 0 to 200 µA to AGND

0.5

ppm/µA

VREF Turn-on Time 1

4.7µF tantalum, 0.1µF ceramic bypass

VREF Turn-on Time 2

0.1µF ceramic bypass

µs

VREF Turn-on Time 3

no bypass cap

µs

EXTERNAL REFERENCE (REFBE = 0)

Input Voltage Range

1.00

(AV+) -

0.3

Input Current

µA

Figure 10.2. REF0CN: Reference Control Register

Bits7-5:

UNUSED. Read = 000b; Write = don't care.

Bit4:

AD0VRS: ADC0 Voltage Reference Select.
0: ADC0 voltage reference from VREFA pin.
1: ADC0 voltage reference from DAC0 output.

Bit3:

AD2VRS: ADC2 Voltage Reference Select.
0: ADC2 voltage reference from VREFA pin.
1: ADC2 voltage reference from AV+.

Bit2:

TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.

Bit1:

BIASE: ADC/DAC Bias Generator Enable Bit. (Must be `1' if using ADC or DAC).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.

Bit0:

REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.

SFR Page:
SFR Address:

0
0xD1

R/W

Reset Value

AD0VRS

AD2VRS

TEMPE

BIASE

REFBE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

DS008-1.1-JUN03

Page 111

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

11.

COMPARATORS

C8051F120/1/2/3/4/5/6/7 devices include two on-chip programmable voltage comparators as shown in Figure 11.1.
The inputs of each Comparator are available at dedicated pins. The output of each comparator is optionally available
at the package pins via the I/O crossbar. When assigned to package pins, each comparator output can be programmed
to operate in open drain or push-pull modes. See

Section "19.1. Ports 0 through 3 and the Priority Crossbar

Decoder" on page 217

for Crossbar and port initialization details.

Figure 11.1. Comparator Functional Block Diagram

SET

CLR

SET

CLR

Crossbar

Interrupt

Handler

Reset

Decision

Tree

(SYNCHRONIZER)

CP0+

CP0-

AGND

CPT

CP0HYN0

CP0HYN1

CP0HYP0

CP0HYP1

CP0FIF

CP0RIF

CP0OUT

CP0EN

AV+

CPT

CP0MD0

CP0MD1

CP0FIE

CP0RIE

CP0MD

SET

CLR

SET

CLR

Crossbar

Interrupt

Handler

(SYNCHRONIZER)

CP1+

CP1-

AGND

CPT

CP1HYN0

1MD

CP1HYN1

CP1HYP0

CP1HYP1

CP1FIF

CP1RIF

CP1OUT

CP1EN

AV+

CPT

CP1MD0

CP1MD1

CP1FIE

CP1RIE

CP1MD

Page 112

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (For interrupt enable
and priority control, see

Section "12.7. Interrupt Handler" on page 146

). The CP0FIF flag is set upon a

Comparator0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator0 rising-edge interrupt. Once set,
these bits remain set until cleared by software. The Output State of Comparator0 can be obtained at any time by read-
ing the CP0OUT bit. Comparator0 is enabled by setting the CP0EN bit to logic 1, and is disabled by clearing this bit
to logic 0. Comparator0 can also be programmed as a reset source; for details, see Section "

14.5. Comparator0

Reset

" on page

169

Note that after being enabled, there is a Power-Up time (listed in Table 11.1) during which the comparator outputs
stabilize. The states of the Rising-Edge and Falling-Edge flags are indeterminant after comparator Power-Up and
should be explicitly cleared before the comparator interrupts are enabled or the comparators are configured as a reset
source.

Comparator0 response time may be configured in software via the CP0MD1-0 bits in register CPT0MD (see
Figure 11.4). Selecting a longer response time reduces the amount of current consumed by Comparator0. See
Table 11.1 for complete timing and current consumption specifications.

The hysteresis of each comparator is software-programmable via its respective Comparator control register (CPT0CN
and CPT1CN for Comparator0 and Comparator1, respectively). The user can program both the amount of hysteresis
voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the
threshold voltage. The output of the comparator can be polled in software, or can be used as an interrupt source. Each
comparator can be individually enabled or disabled (shutdown). When disabled, the comparator output (if assigned to
a Port I/O pin via the Crossbar) defaults to the logic low state, its interrupt capability is suspended and its supply cur-
rent falls to less than 100 nA. Comparator inputs can be externally driven from -0.25 V to (AV+) + 0.25 V without
damage or upset.

Comparator0 hysteresis is programmed using bits 3-0 in the Comparator0 Control Register CPT0CN (shown in
Figure 11.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As shown
in Figure 11.3, the negative hysteresis can be programmed to three different settings, or negative hysteresis can be
disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.

The operation of Comparator1 is identical to that of Comparator0, though Comparator1 may not be configured as a
reset source. Comparator1 is controlled by the CPT1CN Register (Figure 11.5) and the CPT1MD Register
(Figure 11.6). The complete electrical specifications for the Comparators are given in Table 11.1.

Page 114

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 11.3. CPT0CN: Comparator0 Control Register

Bit7:

CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.

Bit6:

CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0-.
1: Voltage on CP0+ > CP0-.

Bit5:

CP0RIF: Comparator0 Rising-Edge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.

Bit4:

CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.

Bits3-2:

CP0HYP1-0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 15 mV.

Bits1-0:

CP0HYN1-0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 15 mV.

SFR Page:
SFR Address:

1
0x88

R/W

Reset Value

CP0EN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Page 116

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 11.5. CPT1CN: Comparator1 Control Register

Bit7:

CP1EN: Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.

Bit6:

CP1OUT: Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1-.
1: Voltage on CP1+ > CP1-.

Bit5:

CP1RIF: Comparator1 Rising-Edge Flag.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.

Bit4:

CP1FIF: Comparator1 Falling-Edge Flag.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge Interrupt has occurred.

Bits3-2:

CP1HYP1-0: Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 15 mV.

Bits1-0:

CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 15 mV.

SFR Page:
SFR Address:

2
0x88

R/W

Reset Value

CP1EN

CP1OUT

CP1RIF

CP1FIF

CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Page 118

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

is the common-mode voltage on CPn+ and CPn-.

Table 11.1. Comparator Electrical Characteristics

VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Response Time:

Mode 0, Vcm

= 1.5 V

CPn+ - CPn- = 100 mV

100

CPn+ - CPn- = -100 mV

250

Response Time:

Mode 1, Vcm

= 1.5 V

CPn+ - CPn- = 100 mV

175

CPn+ - CPn- = -100 mV

500

Response Time:

Mode 2, Vcm

= 1.5 V

CPn+ - CPn- = 100 mV

320

CPn+ - CPn- = -100 mV

1100

Response Time:

Mode 3, Vcm

= 1.5 V

CPn+ - CPn- = 100 mV

1050

CPn+ - CPn- = -100 mV

5200

Common-Mode Rejection Ratio

1.5

mV/V

Positive Hysteresis 1

CPnHYP1-0 = 00

Positive Hysteresis 2

CPnHYP1-0 = 01

4.5

Positive Hysteresis 3

CPnHYP1-0 = 10

Positive Hysteresis 4

CPnHYP1-0 = 11

Negative Hysteresis 1

CPnHYN1-0 = 00

Negative Hysteresis 2

CPnHYN1-0 = 01

4.5

Negative Hysteresis 3

CPnHYN1-0 = 10

Negative Hysteresis 4

CPnHYN1-0 = 11

Inverting or Non-Inverting Input
Voltage Range

-0.25

(AV+)
+ 0.25

Input Capacitance

Input Bias Current

-5

0.001

Input Offset Voltage

-10

+10

POWER SUPPLY

Power-up Time

CPnEN from 0 to 1

µs

Power Supply Rejection

0.1

mV/V

Supply Current at DC (each
comparator)

Mode 0

7.6

µA

Mode 1

3.2

µA

Mode 2

1.3

µA

Mode 3

0.4

µA

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12.

CIP-51 MICROCONTROLLER

The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51TM
instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has
a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see descrip-
tion in

Section 24

), two full-duplex UARTs (see description in

Section 22

and

Section 23

), 256 bytes of internal

RAM, 128 byte Special Function Register (SFR) address space (see

Section 12.2.6

), and 8/4 byte-wide I/O Ports (see

description in

Section 19

). The CIP-51 also includes on-chip debug hardware (see description in

Section 26

), and

interfaces directly with the MCU's analog and digital subsystems providing a complete data acquisition or control-
system solution in a single integrated circuit.

The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional
custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes
the following features:

Figure 12.1. CIP-51 Block Diagram

DATA BUS

TMP1

TMP2

PRGM. ADDRESS REG.

PC INCREMENTER

ALU

PSW

DATA BUS

MEMORY

INTERFACE

MEM_ADDRESS

PIPELINE

BUFFER

DATA POINTER

INTERRUPT
INTERFACE

SYSTEM_IRQs

EMULATION_IRQ

MEM_CONTROL

CONTROL

LOGIC

A16

PROGRAM COUNTER (PC)

STOP

CLOCK

RESET

IDLE

POWER CONTROL

SFR
BUS

INTERFACE

SFR_ADDRESS

SFR_CONTROL

SFR_WRITE_DATA

SFR_READ_DATA

B REGISTER

ACCUMULATOR

MEM_WRITE_DATA

MEM_READ_DATA

SRAM

ADDRESS

SRAM

(256 X 8)

STACK POINTER

Fully Compatible with MCS-51 Instruction Set

100 or 50 MIPS Peak Using the On-Chip PLL

256 Bytes of Internal RAM

8/4 Byte-Wide I/O Ports

Extended Interrupt Handler

Reset Input

Power Management Modes

On-chip Debug Logic

Program and Data Memory Security

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Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to exe-
cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc-
tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles.

With the CIP-51's system clock running at 100 MHz, it has a peak throughput of 100 MIPS. The CIP-51 has a total of
109 instructions. The table below shows the total number of instructions that require each execution time.

Programming and Debugging Support
A JTAG-based serial interface is provided for in-system programming of the FLASH program memory and commu-
nication with on-chip debug support logic. The re-programmable FLASH can also be read and changed by the appli-
cation software using the MOVC and MOVX instructions. This feature allows program memory to be used for non-
volatile data storage as well as updating program code under software control.

The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware break-
points and watch points, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and memory. This
method of on-chip debug is completely non-intrusive and non-invasive, requiring no RAM, Stack, timers, or other
on-chip resources.

The CIP-51 is supported by development tools from Cygnal Integrated Products and third party vendors. Cygnal pro-
vides an integrated development environment (IDE) including editor, macro assembler, debugger and programmer.
The IDE's debugger and programmer interface to the CIP-51 via its JTAG interface to provide fast and efficient in-
system device programming and debugging. Third party macro assemblers and C compilers are also available.

12.1.

Instruction Set

The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51TM instruction set;
standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the
binary and functional equivalent of their MCS-51TM counterparts, including opcodes, addressing modes and effect on
PSW flags. However, instruction timing is different than that of the standard 8051.

12.1.1. Instruction and CPU Timing

In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with machine cycles
varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based solely on clock cycle tim-
ing. All instruction timings are specified in terms of clock cycles.

Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock cycles as there
are program bytes in the instruction. Conditional branch instructions take one less clock cycle to complete when the
branch is not taken as opposed to when the branch is taken. Table 12.1 is the CIP-51 Instruction Set Summary, which
includes the mnemonic, number of bytes, and number of clock cycles for each instruction.

12.1.2. MOVX Instruction and Program Memory

In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip XRAM,
and accessing on-chip program FLASH memory. The FLASH access feature provides a mechanism for user software
to update program code and use the program memory space for non-volatile data storage (see

Section "16. FLASH

Clocks to Execute

2/3

3/4

4/5

Number of Instructions

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MEMORY" on page 185

). The External Memory Interface provides a fast access to off-chip XRAM (or memory-

mapped peripherals) via the MOVX instruction. Refer to

Section "18. EXTERNAL DATA MEMORY INTER-

FACE AND ON-CHIP XRAM" on page 199

for details.

Table 12.1. CIP-51 Instruction Set Summary

Mnemonic

Description

Bytes

Clock

Cycles

ARITHMETIC OPERATIONS

ADD A, Rn

Add register to A

ADD A, direct

Add direct byte to A

ADD A, @Ri

Add indirect RAM to A

ADD A, #data

Add immediate to A

ADDC A, Rn

Add register to A with carry

ADDC A, direct

Add direct byte to A with carry

ADDC A, @Ri

Add indirect RAM to A with carry

ADDC A, #data

Add immediate to A with carry

SUBB A, Rn

Subtract register from A with borrow

SUBB A, direct

Subtract direct byte from A with borrow

SUBB A, @Ri

Subtract indirect RAM from A with borrow

SUBB A, #data

Subtract immediate from A with borrow

INC A

Increment A

INC Rn

Increment register

INC direct

Increment direct byte

INC @Ri

Increment indirect RAM

DEC A

Decrement A

DEC Rn

Decrement register

DEC direct

Decrement direct byte

DEC @Ri

Decrement indirect RAM

INC DPTR

Increment Data Pointer

MUL AB

Multiply A and B

DIV AB

Divide A by B

DA A

Decimal adjust A

LOGICAL OPERATIONS

ANL A, Rn

AND Register to A

ANL A, direct

AND direct byte to A

ANL A, @Ri

AND indirect RAM to A

ANL A, #data

AND immediate to A

ANL direct, A

AND A to direct byte

ANL direct, #data

AND immediate to direct byte

ORL A, Rn

OR Register to A

ORL A, direct

OR direct byte to A

ORL A, @Ri

OR indirect RAM to A

ORL A, #data

OR immediate to A

ORL direct, A

OR A to direct byte

ORL direct, #data

OR immediate to direct byte

XRL A, Rn

Exclusive-OR Register to A

XRL A, direct

Exclusive-OR direct byte to A

XRL A, @Ri

Exclusive-OR indirect RAM to A

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XRL A, #data

Exclusive-OR immediate to A

XRL direct, A

Exclusive-OR A to direct byte

XRL direct, #data

Exclusive-OR immediate to direct byte

CLR A

Clear A

CPL A

Complement A

RL A

Rotate A left

RLC A

Rotate A left through Carry

RR A

Rotate A right

RRC A

Rotate A right through Carry

SWAP A

Swap nibbles of A

DATA TRANSFER

MOV A, Rn

Move Register to A

MOV A, direct

Move direct byte to A

MOV A, @Ri

Move indirect RAM to A

MOV A, #data

Move immediate to A

MOV Rn, A

Move A to Register

MOV Rn, direct

Move direct byte to Register

MOV Rn, #data

Move immediate to Register

MOV direct, A

Move A to direct byte

MOV direct, Rn

Move Register to direct byte

MOV direct, direct

Move direct byte to direct byte

MOV direct, @Ri

Move indirect RAM to direct byte

MOV direct, #data

Move immediate to direct byte

MOV @Ri, A

Move A to indirect RAM

MOV @Ri, direct

Move direct byte to indirect RAM

MOV @Ri, #data

Move immediate to indirect RAM

MOV DPTR, #data16

Load DPTR with 16-bit constant

MOVC A, @A+DPTR

Move code byte relative DPTR to A

MOVC A, @A+PC

Move code byte relative PC to A

MOVX A, @Ri

Move external data (8-bit address) to A

MOVX @Ri, A

Move A to external data (8-bit address)

MOVX A, @DPTR

Move external data (16-bit address) to A

MOVX @DPTR, A

Move A to external data (16-bit address)

PUSH direct

Push direct byte onto stack

POP direct

Pop direct byte from stack

XCH A, Rn

Exchange Register with A

XCH A, direct

Exchange direct byte with A

XCH A, @Ri

Exchange indirect RAM with A

XCHD A, @Ri

Exchange low nibble of indirect RAM with A

BOOLEANMANIPULATION

CLR C

Clear Carry

CLR bit

Clear direct bit

SETB C

Set Carry

SETB bit

Set direct bit

CPL C

Complement Carry

Table 12.1. CIP-51 Instruction Set Summary

Mnemonic

Description

Bytes

Clock

Cycles

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CPL bit

Complement direct bit

ANL C, bit

AND direct bit to Carry

ANL C, /bit

AND complement of direct bit to Carry

ORL C, bit

OR direct bit to carry

ORL C, /bit

OR complement of direct bit to Carry

MOV C, bit

Move direct bit to Carry

MOV bit, C

Move Carry to direct bit

JC rel

Jump if Carry is set

2/3

JNC rel

Jump if Carry is not set

2/3

JB bit, rel

Jump if direct bit is set

3/4

JNB bit, rel

Jump if direct bit is not set

3/4

JBC bit, rel

Jump if direct bit is set and clear bit

3/4

PROGRAM BRANCHING

ACALL addr11

Absolute subroutine call

LCALL addr16

Long subroutine call

RET

Return from subroutine

RETIReturn from interrupt

AJMP addr11

Absolute jump

LJMP addr16

Long jump

SJMP rel

Short jump (relative address)

JMP @A+DPTR

Jump indirect relative to DPTR

JZ rel

Jump if A equals zero

2/3

JNZ rel

Jump if A does not equal zero

2/3

CJNE A, direct, rel

Compare direct byte to A and jump if not equal

3/4

CJNE A, #data, rel

Compare immediate to A and jump if not equal

3/4

CJNE Rn, #data, rel

Compare immediate to Register and jump if not equal

3/4

CJNE @Ri, #data, rel

Compare immediate to indirect and jump if not equal

4/5

DJNZ Rn, rel

Decrement Register and jump if not zero

2/3

DJNZ direct, rel

Decrement direct byte and jump if not zero

3/4

NOP

No operation

Table 12.1. CIP-51 Instruction Set Summary

Mnemonic

Description

Bytes

Clock

Cycles

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Notes on Registers, Operands and Addressing Modes:

Rn - Register R0-R7 of the currently selected register bank.

@Ri - Data RAM location addressed indirectly through R0 or R1.

rel - 8-bit, signed (two's complement) offset relative to the first byte of the following instruction. Used by SJMP
and all conditional jumps.

direct - 8-bit internal data location's address. This could be a direct-access Data RAM location (0x00-0x7F) or an
SFR (0x80-0xFF).

#data - 8-bit constant

#data16 - 16-bit constant

bit - Direct-accessed bit in Data RAM or SFR

addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-byte
page of program memory as the first byte of the following instruction.

addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the 64K-
byte program memory space.

There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.

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12.2.

Memory Organization

The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa-
rate memory spaces: program memory and data memory. Program and data memory share the same address space but
are accessed via different instruction types. There are 256 bytes of internal data memory and 128k bytes of internal
program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in
Figure 12.2.

12.2.1. Program Memory

The CIP-51 has a 128k byte program memory space. The MCU implements 131072 bytes of this program memory
space as in-system re-programmable FLASH memory in four 32k byte code banks. A common code bank (Bank 0)
of 32k bytes is always accessible from addresses 0x0000 to 0x7FFF. The three upper code banks (Bank 1, Bank 2,
and Bank 3) are each mapped to addresses 0x8000 to 0xFFFF, depending on the selection of bits in the PSBANK reg-
ister, as described in Figure 12.3. The IFBANK bits select which of the upper banks are used for code execution,
while the COBANK bits select the bank to be used for direct writes and reads of the FLASH memory. Note: 1024
bytes of the memory in Bank 3 (0x1FC00 to 0x1FFFF) are reserved and are not available for user program or data
storage.

Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting
the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism
for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to

Sec-

tion "16. FLASH MEMORY" on page 185

for further details.

PROGRAM/DATA MEMORY

(FLASH)

(Directand Indirect

Addressing)

0x00

0x7F

Upper 128 RAM

(IndirectAddressing

Only)

0x80

0xFF

DATA MEMORY (RAM)

General Purpose

Registers

0x1F

0x20

0x2F

BitAddressable

0x30

INTERNAL DATA ADDRESS SPACE

EXTERNAL DATA ADDRESS SPACE

XRAM - 8192 Bytes

(accessable using MOVX

instruction)

0x0000

0x1FFF

Off-chip XRAM space

0x2000

0xFFFF

FLASH

(In-System

Programmable in 1024

Byte Sectors)

0x00000

0x1FFFF

RESERVED

0x1FC00

0x1FBFF

Scrachpad Memory

(DATA only)

0x200FF

0x20000

Special Function

Registers

(DirectAddressing Only)

Lower 128 RAM
(Directand Indirect
Addressing)

Up To

256 SFR Pages

Figure 12.2. Memory Map

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Figure 12.3. PSBANK: Program Space Bank Select Register

Bits 7-6:

Reserved.

Bits 5-4:

COBANK: Constant Operations Bank Select.
These bits select which FLASH bank is targeted during constant operations (MOVC and FLASH
MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the Scratch-
pad memory areas (see

Section "16. FLASH MEMORY" on page 185

00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between 0x0000 to 0x7FFF).
01: Constant Operations Target Bank 1.
10: Constant Operations Target Bank 2.
11: Constant Operations Target Bank 3.

Bits 3-2:

Reserved.

Bits 1-0:

IFBANK: Instruction Fetch Operations Bank Select.
These bits select which FLASH bank is used for instruction fetches involving addresses 0x8000 to
0xFFFF. These bits can only be changed from code in Bank 0 (see Figure 12.4).
00: Instructions Fetch From Bank 0 (note that Bank 0 is also mapped between 0x0000 to 0x7FFF).
01: Instructions Fetch From Bank 1.
10: Instructions Fetch From Bank 2.
11: Instructions Fetch From Bank 3.

R/W

Reset Value

COBANK

IFBANK

00010001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xB1
All Pages

Bank 0

Bank 1

Bank 2

Bank 3

Bank 0

IFBANK = 0

IFBANK = 1

IFBANK = 2

IFBANK = 3

Internal

Address

0x0000

0x7FFF

0x8000

0xFFFF

Figure 12.4. Address Memory Map for Instruction Fetches

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12.2.2. Data Memory

The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and memory. Either direct or indirect
addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable
as four banks of general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, loca-
tions 0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct address-
ing mode.

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the same
address space as the Special Function Registers (SFR) but is physically separate from the SFR space. The addressing
mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper
128 bytes of data memory space or the SFR's. Instructions that use direct addressing will access the SFR space.
Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory. Figure 12.2 illustrates
the data memory organization of the CIP-51.

12.2.3. General Purpose Registers

The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose
registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only one of these banks may be
enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1 (PSW.4), select the active register bank
(see description of the PSW in Figure 12.18). This allows fast context switching when entering subroutines and inter-
rupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.

12.2.4. Bit Addressable Locations

In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through
0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of
the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has
bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or
destination operands as opposed to a byte source or destination).

The MCS-51TM assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the
byte address and B is the bit position within the byte. For example, the instruction:

MOV

C, 22.3h

moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.

12.2.5. Stack

A programmer's stack can be located anywhere in the 256 byte data memory. The stack area is designated using the
Stack Pointer (SP, address 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack
is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location 0x07; therefore, the first
value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if
more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used
for data storage. The stack depth can extend up to 256 bytes.

The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a
32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, and each CALL
pushes two record bits onto the register. (A POP or decrement SP pops one record bit, and a RET pops two record
bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can
notify the debug software even with the MCU running at speed.

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12.2.6. Special Function Registers

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFR's). The
SFR's provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the
SFR's found in a typical 8051 implementation as well as implementing additional SFR's used to configure and access
the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with
the MCS-51TM instruction set. Table 12.2 lists the SFR's implemented in the CIP-51 System Controller.

The SFR registers are accessed whenever the direct addressing mode is used to access memory locations from 0x80
to 0xFF. SFR's with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well
as byte-addressable. All other SFR's are byte-addressable only. Unoccupied addresses in the SFR space are reserved
for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the corre-
sponding pages of the datasheet, as indicated in Table 12.3, for a detailed description of each register.

12.2.6.1. SFR Paging

The CIP-51 features SFR paging, allowing the device to map many SFR's into the 0x80 to 0xFF memory address
space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to 0xFF can access up to
256 SFR's. The C8051F12x family of devices utilizes five SFR pages: 0, 1, 2, 3, and F. SFR pages are selected using
the Special Function Register Page Selection register, SFRPAGE (see Figure 12.12). The procedure for reading and
writing an SFR is as follows:

Select the appropriate SFR page number using the SFRPAGE register.

Use direct accessing mode to read or write the special function register (MOV instruction).

12.2.6.2. Interrupts and SFR Paging

When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page containing the flag bit
that caused the interrupt. The automatic SFR Page switch function conveniently removes the burden of switching
SFR pages from the interrupt service routine. Upon execution of the RETIinstruction, the SFR page is automatically
restored to the SFR Page in use prior to the interrupt. This is accomplished via a three-byte SFR Page Stack. The top
byte of the stack is SFRPAGE, the current SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The third,
or bottom byte of the SFR Page Stack is SFRLAST. On interrupt, the current SFRPAGE value is pushed to the SFRN-
EXT byte, and the value of SFRNEXT is pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page
containing the flag bit associated with the interrupt. On a return from interrupt, the SFR Page Stack is popped result-
ing in the value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR page context without
software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the
stack is placed in SFRNEXT register. If desired, the values stored in SFRNEXT and SFRLAST may be modified dur-
ing an interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETIinstruction (on inter-
rupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of the stack. Only interrupt calls
and returns will cause push/pop operations on the SFR Page Stack.

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12.2.6.3. SFR Page Stack Example

The following is an example that shows the operation of the SFR Page Stack during interrupts.

In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is exe-
cuting in-line code that is writing values to Port 5 (SFR "P5", located at address 0xD8 on SFR Page 0x0F). The
device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC2) window comparator to
monitor a voltage. The PCA is timing a critical control function in its interrupt service routine (ISR), so its interrupt is
enabled and is set to high priority. The ADC2 is monitoring a voltage that is less important, but to minimize the soft-
ware overhead its window comparator is being used with an associated ISR that is set to low priority. At this point, the
SFR page is set to access the Port 5 SFR (SFRPAGE = 0x0F). See Figure 12.6 below.

0x0F

(Port5)

SFRPAGE

SFRLAST

SFRNEXT

SFR Page

Stack SFR's

Figure 12.6. SFR Page Stack While Using SFR Page 0x0F To Access Port 5

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While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt,
while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high prior-
ity PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to access the PCA's special
function registers into the SFRPAGE register, SFR Page 0x00. The value that was in the SFRPAGE register before
the PCA interrupt (SFR Page 2 for ADC2) is pushed down the stack into SFRNEXT. Likewise, the value that was in
the SFRNEXT register before the PCA interrupt (in this case SFR Page 0x0F for Port 5) is pushed down to the SFR-
LAST register, the "bottom" of the stack. Note that a value stored in SFRLAST (via a previous software write to the
SFRLAST register) will be overwritten. See Figure 12.8 below.

0x00

(PCA)

0x02

(ADC2)

0x0F

(Port5)

SFRPAGE

SFRLAST

SFRNEXT

SFR Page 0x00

Automatically

pushed on stack in

SFRPAGE on PCA

interrupt

SFRPAGE

pushed to

SFRNEXT

pushed to

SFRLAST

Figure 12.8. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR

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On the execution of the RETIinstruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is
overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as it did prior to the
interrupts occurring. See Figure 12.10 below.

Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT,
and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to return to
a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to the SFR Page stack
can be useful to enable real-time operating systems to control and manage context switching between multiple tasks.

Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on interrupt
exit (execution on the RETIinstruction). The automatic switching of the SFRPAGE and operation of the SFR Page
Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in
the SFR Page Control Register (SFRPGCN). See Figure 12.11.

0x0F

(Port5)

SFRPAGE

SFRLAST

SFRNEXT

SFR Page 0x02

Automatically

popped off of the

stack on return from

interrupt

SFRNEXT

popped to

SFRPAGE

Figure 12.10. SFR Page Stack Upon Return From ADC2 Window Interrupt

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 12.11. SFRPGCN: SFR Page Control Register

Bits7-1:

Reserved.

Bit0:

SFRPGEN: SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and automati-
cally switch the SFR page to the corresponding peripheral or function's SFR page. This bit is used to
control this autopaging function.
0: SFR Automatic Paging disabled. C8051 core will not automatically change to the appropriate SFR
page (i.e., the SFR page that contains the SFR's for the peripheral/function that was the source of the
interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will switch the SFR page to the page
that contains the SFR's for the peripheral or function that is the source of the interrupt.

R/W

Reset Value

SFRPGEN 00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x96
F

Figure 12.12. SFRPAGE: SFR Page Register

Bits7-0:

SFR Page Bits: Byte Represents the SFR Page the C8051 MCU uses when reading or modifying
SFR's.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 MCU is using.

When enabled in the SFR Page Control Register (SFRPGCN), the C8051 will automatically switch to
the SFR Page that contains the SFR's of the corresponding peripheral/function that caused the inter-
rupt, and return to the previous SFR page upon return from interrupt (unless SFR Stack was altered
before a returning from the interrupt).
SFRPAGE is the top byte of the SFR Page Stack, and push/pop events of this stack are caused by
interrupts (and not by reading/writing to the SFRPAGE register)

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x84
All Pages

Page 136

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 12.13. SFRNEXT: SFR Next Register

Bits7-0:

SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFRLAST is the third
entry. The SFR stack bytes may be used alter the context in the SFR Page Stack, and will not cause
the stack to `push' or `pop'. Only interrupts and return from interrupts cause pushes and pops of the
SFR Page Stack.

Write:

Sets the SFR Page contained in the second byte of the SFR Stack. This will cause the

SFRPAGE SFR to have this SFR page value upon a return from interrupt.

Read:

Returns the value of the SFR page contained in the second byte of the SFR stack. This is the

value that will go to the SFR Page register upon a return from interrupt.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x85
All Pages

Figure 12.14. SFRLAST: SFR Last Register

Bits7-0:

Write:

Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to

have this SFR page value upon a return from interrupt.

Read:

Returns the value of the SFR page contained in the last entry of the SFR stack.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x86
All Pages

DS008-1.1-JUN03

Page 137

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 12.2. Special Function Register (SFR) Memory Map

SFR

Pag

0(8)

1(9)

2(A)

3(B)

4(C)

5(D)

6(E)

7(F)

0
1
2
3
F

SPI0CN

PCA0L

PCA0H

PCA0CPL0

PCA0CPH0

PCA0CPL1

PCA0CPH1

WDTCN

(ALL

PAGES)

0
1
2
3
F

(ALL

PAGES)

EIP1

(ALL

PAGES)

EIP2

(ALL

PAGES)

0
1
2
3
F

ADC0CN

ADC2CN

PCA0CPL2

PCA0CPH2

PCA0CPL3

PCA0CPH3

PCA0CPL4

PCA0CPH4

RSTSRC

0
1
2
3
F

ACC

(ALL

PAGES)

PCA0CPL5

XBR0

PCA0CPH5

XBR1

XBR2

EIE1

(ALL

PAGES)

EIE2

(ALL

PAGES)

0
1
2
3
F

PCA0CN

PCA0MD

PCA0CPM0

PCA0CPM1

PCA0CPM2

PCA0CPM3

PCA0CPM4

PCA0CPM5

0
1
2
3
F

PSW

(ALL

PAGES)

REF0CN

DAC0L
DAC1L

DAC0H
DAC1H

DAC0CN
DAC1CN

0
1
2
3
F

TMR2CN
TMR3CN
TMR4CN

TMR2CF
TMR3CF
TMR4CF

RCAP2L
RCAP3L
RCAP4L

RCAP2H
RCAP3H
RCAP4H

TMR2L
TMR3L
TMR4L

TMR2H
TMR3H
TMR4H

SMB0CR

0
1
2
3
F

SMB0CN

MAC0STA

SMB0STA

MAC0AL

SMB0DAT

MAC0AH

SMB0ADR

MAC0CF

ADC0GTL

ADC2GT

ADC0GTH

ADC0LTL

ADC2LT

MAC0RNDL

ADC0LTH

MAC0RNDH

0
1
2
3
F

(ALL

PAGES)

SADEN0

AMX0CF

AMX2CF

AMX0SL

AMX2SL

ADC0CF

ADC2CF

ADC0L

ADC2

ADC0H

0(8)

1(9)

2(A)

3(B)

4(C)

5(D)

6(E)

7(F)

Page 138

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

0
1
2
3
F

(ALL

PAGES)

PSBANK

(ALL

PAGES)

FLSCL

FLACL

0
1
2
3
F

(ALL

PAGES)

SADDR0

P1MDIN

0
1
2
3
F

(ALL

PAGES)

EMI0TC

CCH0CN

EMI0CN

CCH0TN

EMI0CF

CCH0LC

P0MDOUT

P1MDOUT

P2MDOUT

P3MDOUT

0
1
2
3
F

SCON0
SCON1

SBUF0
SBUF1

SPI0CFG

CCH0MA

SPI0DAT

P4MDOUT

SPI0CKR

P5MDOUT

P6MDOUT

P7MDOUT

0
1
2
3
F

(ALL

PAGES)

SSTA0

MAC0BL

MAC0BH

MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3

SFRPGCN

MAC0OVR

CLKSEL

0
1
2
3
F

TCON

CPT0CN
CPT1CN

FLSTAT

TMOD

CPT0MD
CPT1MD

PLL0CN

TL0

OSCICN

TL1

OSCICL

TH0

OSCXCN

TH1

PLL0DIV

CKCON

PLL0MUL

PSCTL

PLL0FLT

0
1
2
3
F

(ALL

PAGES)

(ALL

PAGES)

DPL

(ALL

PAGES)

DPH

(ALL

PAGES)

SFRPAGE

(ALL

PAGES)

SFRNEXT

(ALL

PAGES)

SFRLAST

(ALL

PAGES)

PCON

(ALL

PAGES)

Table 12.3. Special Function Registers

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

SFR

Page

Description

Page No.

ACC

0xE0

All Pages Accumulator

page 145

ADC0CF

0xBC

ADC0 Configuration

page 56*, page 74**

ADC0CN

0xE8

ADC0 Control

page 57*, page 75**

ADC0GTH

0xC5

ADC0 Greater-Than High Byte

page 60*, page 78**

ADC0GTL

0xC4

ADC0 Greater-Than Low Byte

page 60*, page 78**

Table 12.2. Special Function Register (SFR) Memory Map

0(8)

1(9)

2(A)

3(B)

4(C)

5(D)

6(E)

7(F)

DS008-1.1-JUN03

Page 139

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

ADC0H

0xBF

ADC0 Data Word High Byte

page 58*, page 76**

ADC0L

0xBE

ADC0 Data Word Low Byte

page 58*, page 76**

ADC0LTH

0xC7

ADC0 Less-Than High Byte

page 61*, page 79**

ADC0LTL

0xC6

ADC0 Less-Than Low Byte

page 61*, page 79**

ADC2

0xBE

ADC2 Data Word

page 93

ADC2CF

0xBC

ADC2 Configuration

page 91

ADC2CN

0xE8

ADC2 Control

page 92

ADC2GT

0xC4

ADC2 Greater-Than

page 96

ADC2LT

0xC6

ADC2 Less-Than

page 96

AMX0CF

0xBA

ADC0 Multiplexer Configuration

page 54*, page 72**

AMX0SL

0xBB

ADC0 Multiplexer Channel Select

page 55*, page 73**

AMX2CF

0xBA

ADC2 Multiplexer Configuration

page 89

AMX2SL

0xBB

ADC2 Multiplexer Channel Select

page 90

0xF0

All Pages B Register

page 145

CCH0CN

0xA1

Cache Control

page 196

CCH0LC

0xA3

Cache Lock

page 197

CCH0MA

0x9A

Cache Miss Accumulator

page 198

CCH0TN

0xA2

Cache Tuning

page 197

CKCON

0x8E

Clock Control

page 291

CLKSEL

0x97

System Clock Select

page 175

CPT0CN

0x88

Comparator 0 Control

page 114

CPT0MD

0x89

Comparator 0 Configuration

page 115

CPT1CN

0x88

Comparator 1 Control

page 116

CPT1MD

0x89

Comparator 1 Configuration

page 117

DAC0CN

0xD4

DAC0 Control

page 102

DAC0H

0xD3

DAC0 High Byte

page 101

DAC0L

0xD2

DAC0 Low Byte

page 101

DAC1CN

0xD4

DAC1 Control

page 104

DAC1H

0xD3

DAC1 High Byte

page 103

DAC1L

0xD2

DAC1 Low Byte

page 103

DPH

0x83

All Pages Data Pointer High Byte

page 143

DPL

0x82

All Pages Data Pointer Low Byte

page 143

EIE1

0xE6

All Pages Extended Interrupt Enable 1

page 151

EIE2

0xE7

All Pages Extended Interrupt Enable 2

page 152

EIP1

0xF6

All Pages Extended Interrupt Priority 1

page 153

EIP2

0xF7

All Pages Extended Interrupt Priority 2

page 154

EMI0CF

0xA3

EMIF Configuration

page 201

EMI0CN

0xA2

EMIF Control

page 201

EMI0TC

0xA1

EMIF Timing Control

page 206

FLACL

0xB7

FLASH Access Limit

page 190

FLSCL

0xB7

FLASH Scale

page 191

FLSTAT

0x88

FLASH Status

page 198

0xA8

All Pages Interrupt Enable

page 149

0xB8

All Pages Interrupt Priority

page 150

Table 12.3. Special Function Registers

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

SFR

Page

Description

Page No.

Page 140

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

MAC0ACC0

0x93

MAC0 Accumulator Byte 0 (LSB)

page 165

MAC0ACC1

0x94

MAC0 Accumulator Byte 1

page 165

MAC0ACC2

0x95

MAC0 Accumulator Byte 2

page 165

MAC0ACC3

0x96

MAC0 Accumulator Byte 3 (MSB)

page 164

MAC0AH

0xC2

MAC0 A Register High Byte

page 163

MAC0AL

0xC1

MAC0 A Register Low Byte

page 164

MAC0BH

0x92

MAC0 B Register High Byte

page 164

MAC0BL

0x91

MAC0 B Register Low Byte

page 164

MAC0CF

0xC3

MAC0 Configuration

page 162

MAC0OVR

0x97

MAC0 Accumulator Overflow

page 165

MAC0RNDH

0xCF

MAC0 Rounding Register High Byte

page 166

MAC0RNDL

0xCE

MAC0 Rounding Register Low Byte

page 166

MAC0STA

0xC0

MAC0 Status Register

page 163

OSCICL

0x8B

Internal Oscillator Calibration

page 174

OSCICN

0x8A

Internal Oscillator Control

page 174

OSCXCN

0x8C

External Oscillator Control

page 176

0x80

All Pages Port 0 Latch

page 227

P0MDOUT

0xA4

Port 0 Output Mode Configuration

page 227

0x90

All Pages Port 1 Latch

page 228

P1MDIN

0xAD

Port 1 Input Mode

page 228

P1MDOUT

0xA5

Port 1 Output Mode Configuration

page 229

0xA0

All Pages Port 2 Latch

page 229

P2MDOUT

0xA6

Port 2 Output Mode Configuration

page 230

0xB0

All Pages Port 3 Latch

page 230

P3MDOUT

0xA7

Port 3 Output Mode Configuration

page 231

0xC8

Port 4 Latch

page 233

P4MDOUT

0x9C

Port 4 Output Mode Configuration

page 233

0xD8

Port 5 Latch

page 234

P5MDOUT

0x9D

Port 5 Output Mode Configuration

page 234

0xE8

Port 6 Latch

page 235

P6MDOUT

0x9E

Port 6 Output Mode Configuration

page 235

0xF8

Port 7 Latch

page 236

P7MDOUT

0x9F

Port 7 Output Mode Configuration

page 236

PCA0CN

0xD8

PCA Control

page 310

PCA0CPH0

0xFC

PCA Module 0 Capture/Compare High Byte

page 314

PCA0CPH1

0xFE

PCA Module 1 Capture/Compare High Byte

page 314

PCA0CPH2

0xEA

PCA Module 2 Capture/Compare High Byte

page 314

PCA0CPH3

0xEC

PCA Module 3 Capture/Compare High Byte

page 314

PCA0CPH4

0xEE

PCA Module 4 Capture/Compare High Byte

page 314

PCA0CPH5

0xE2

PCA Module 5 Capture/Compare High Byte

page 314

PCA0CPL0

0xFB

PCA Module 0 Capture/Compare Low Byte

page 314

PCA0CPL1

0xFD

PCA Module 1 Capture/Compare Low Byte

page 314

PCA0CPL2

0xE9

PCA Module 2 Capture/Compare Low Byte

page 314

PCA0CPL3

0xEB

PCA Module 3 Capture/Compare Low Byte

page 314

Table 12.3. Special Function Registers

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

SFR

Page

Description

Page No.

DS008-1.1-JUN03

Page 141

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

PCA0CPL4

0xED

PCA Module 4 Capture/Compare Low Byte

page 314

PCA0CPL5

0xE1

PCA Module 5 Capture/Compare Low Byte

page 314

PCA0CPM0

0xDA

PCA Module 0 Mode

page 312

PCA0CPM1

0xDB

PCA Module 1 Mode

page 312

PCA0CPM2

0xDC

PCA Module 2 Mode

page 312

PCA0CPM3

0xDD

PCA Module 3 Mode

page 312

PCA0CPM4

0xDE

PCA Module 4 Mode

page 312

PCA0CPM5

0xDF

PCA Module 5 Mode

page 312

PCA0H

0xFA

PCA Counter High Byte

page 313

PCA0L

0xF9

PCA Counter Low Byte

page 313

PCA0MD

0xD9

PCA Mode

page 311

PCON

0x87

All Pages Power Control

page 156

PLL0CN

0x89

PLL Control

page 180

PLL0DIV

0x8D

PLL Divider

page 180

PLL0FLT

0x8F

PLL Filter

page 181

PLL0MUL

0x8E

PLL Multiplier

page 181

PSBANK

0xB1

All Pages FLASH Bank Select

page 126

PSCTL

0x8F

FLASH Write/Erase Control

page 192

PSW

0xD0

All Pages Program Status Word

page 144

RCAP2H

0xCB

Timer/Counter 2 Capture/Reload High Byte

page 299

RCAP2L

0xCA

Timer/Counter 2 Capture/Reload Low Byte

page 299

RCAP3H

0xCB

Timer 3 Capture/Reload High Byte

page 299

RCAP3L

0xCA

Timer 3 Capture/Reload Low Byte

page 299

RCAP4H

0xCB

Timer/Counter 4 Capture/Reload High Byte

page 299

RCAP4L

0xCA

Timer/Counter 4 Capture/Reload Low Byte

page 299

REF0CN

0xD1

Voltage Reference Control

page 108, page 110

RSTSRC

0xEF

Reset Source

page 171

SADDR0

0xA9

UART 0 Slave Address

page 273

SADEN0

0xB9

UART 0 Slave Address Mask

page 273

SBUF0

0x99

UART 0 Data Buffer

page 273

SBUF1

0x99

UART 1 Data Buffer

page 281

SCON0

0x98

UART 0 Control

page 271

SCON1

0x98

UART 1 Control

page 280

SFRLAST

0x86

All Pages SFR Stack Last Page

page 136

SFRNEXT

0x85

All Pages SFR Stack Next Page

page 136

SFRPAGE

0x84

All Pages SFR Page Select

page 135

SFRPGCN

0x96

SFR Page Control

page 135

SMB0ADR

0xC3

SMBus Slave Address

page 245

SMB0CN

0xC0

SMBus Control

page 243

SMB0CR

0xCF

SMBus Clock Rate

page 244

SMB0DAT

0xC2

SMBus Data

page 245

SMB0STA

0xC1

SMBus Status

page 246

0x81

All Pages Stack Pointer

page 143

SPI0CFG

0x9A

SPI Configuration

page 256

Table 12.3. Special Function Registers

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

SFR

Page

Description

Page No.

Page 142

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

SPI0CKR

0x9D

SPI Clock Rate Control

page 258

SPI0CN

0xF8

SPI Control

page 257

SPI0DAT

0x9B

SPI Data

page 259

SSTA0

0x91

UART 0 Status

page 272

TCON

0x88

Timer/Counter Control

page 289

TH0

0x8C

Timer/Counter 0 High Byte

page 292

TH1

0x8D

Timer/Counter 1 High Byte

page 292

TL0

0x8A

Timer/Counter 0 Low Byte

page 292

TL1

0x8B

Timer/Counter 1 Low Byte

page 292

TMOD

0x89

Timer/Counter Mode

page 290

TMR2CF

0xC9

Timer/Counter 2 Configuration

page 298

TMR2CN

0xC8

Timer/Counter 2 Control

page 298

TMR2H

0xCD

Timer/Counter 2 High Byte

page 300

TMR2L

0xCC

Timer/Counter 2 Low Byte

page 299

TMR3CF

0xC9

Timer 3 Configuration

page 298

TMR3CN

0xC8

Timer 3 Control

page 298

TMR3H

0xCD

Timer 3 High Byte

page 300

TMR3L

0xCC

Timer 3 Low Byte

page 299

TMR4CF

0xC9

Timer/Counter 4 Configuration

page 298

TMR4CN

0xC8

Timer/Counter 4 Control

page 298

TMR4H

0xCD

Timer/Counter 4 High Byte

page 300

TMR4L

0xCC

Timer/Counter 4 Low Byte

page 299

WDTCN

0xFF

All Pages Watchdog Timer Control

page 170

XBR0

0xE1

Port I/O Crossbar Control 0

page 224

XBR1

0xE2

Port I/O Crossbar Control 1

page 225

XBR2

0xE3

Port I/O Crossbar Control 2

page 226

* Refers to a register in the C8051F120/1/4/5 only.
** Refers to a register in the C8051F122/3/6/7 only.
Refers to a register in the C8051F120/2/4/6 only.
Refers to a register in the C8051F121/3/5/7 only.

Table 12.3. Special Function Registers

SFRs are listed in alphabetical order. All undefined SFR locations are reserved.

Register

Address

SFR

Page

Description

Page No.

DS008-1.1-JUN03

Page 143

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

12.6.4. Register Descriptions

Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not
be set to logic l. Future product versions may use these bits to implement new features in which case the reset value
of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of the remaining SFRs are included
in the sections of the datasheet associated with their corresponding system function.

Figure 12.15. SP: Stack Pointer

Bits7-0:

SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented before
every PUSH operation. The SP register defaults to 0x07 after reset.

R/W

Reset Value

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x81
All Pages

Figure 12.16. DPL: Data Pointer Low Byte

Bits7-0:

DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly addressed
XRAM and FLASH memory.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x82
All Pages

Figure 12.17. DPH: Data Pointer High Byte

Bits7-0:

DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed
XRAM and FLASH memory.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x83
All Pages

Page 144

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 12.18. PSW: Program Status Word

Bit7:

CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtrac-
tion). It is cleared to 0 by all other arithmetic operations.

Bit6:

AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from
(subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.

Bit5:

F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.

Bits4-3:

RS1-RS0: Register Bank Select.
These bits select which register bank is used during register accesses.

Bit2:

OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
· An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
· A MUL instruction results in an overflow (result is greater than 255).
· A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.

Bit1:

F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.

Bit0:

PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even.

R/W

Reset Value

RS1

RS0

PARITY

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xD0
All Pages

RS1

RS0

Address

0x00 - 0x07

0x08 - 0x0F

0x10 - 0x17

0x18 - 0x1F

Page 146

DS008-1.1-JUN03

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

12.7.

Interrupt Handler

The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two priority levels.
The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the spe-
cific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an
SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is
set to logic 1.

If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As
soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to
begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns pro-
gram execution to the next instruction that would have been executed if the interrupt request had not occurred. If
interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as
normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)

Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in
an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the
individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of
the individual interrupt-enable settings.

Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However,
most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interrupt-
pending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt
request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction.

12.7.1. MCU Interrupt Sources and Vectors

The MCUs support 20 interrupt sources. Software can simulate an interrupt event by setting any interrupt-pending
flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to
the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, prior-
ity order and control bits are summarized in Table 12.4. Refer to the datasheet section associated with a particular on-
chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its inter-
rupt-pending flag(s).

12.7.2. External Interrupts

Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low
edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1
(TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or
/INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically
cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending
flag follows the state of the external interrupt's input pin. The external interrupt source must hold the input active until
the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes
or another interrupt request will be generated.

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Table 12.4. Interrupt Summary

Interrupt Source

Interrupt

Vector

Priority

Order

Pending Flags

Bit

ddr

essa

Clea

r
e

Enable
Flag

Priority
Control

Reset

0x0000

Top

None

N/A

Always
Enabled

Always
Highest

External Interrupt 0 (/INT0)

0x0003

IE0 (TCON.1)

EX0 (IE.0)

PX0 (IP.0)

Timer 0 Overflow

0x000B

TF0 (TCON.5)

ET0 (IE.1)

PT0 (IP.1)

External Interrupt 1 (/INT1)

0x0013

IE1 (TCON.3)

EX1 (IE.2)

PX1 (IP.2)

Timer 1 Overflow

0x001B

TF1 (TCON.7)

ET1 (IE.3)

PT1 (IP.3)

UART0

0x0023

RI0 (SCON0.0)
TI0 (SCON0.1)

ES0 (IE.4)

PS0 (IP.4)

Timer 2

0x002B

TF2 (TMR2CN.7)
EXF2 (TMR2CN.6)

ET2 (IE.5)

PT2 (IP.5)

Serial Peripheral Interface

0x0033

SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)

ESPI0
(EIE1.0)

PSPI0
(EIP1.0)

SMBus Interface

0x003B

SI (SMB0CN.3)

ESMB0
(EIE1.1)

PSMB0
(EIP1.1)

ADC0 Window Comparator

0x0043

AD0WINT
(ADC0CN.1)

EWADC0
(EIE1.2)

PWADC0
(EIP1.2)

PCA 0

0x004B

CF (PCA0CN.7)
CCFn (PCA0CN.n)

EPCA0
(EIE1.3)

PPCA0
(EIP1.3)

Comparator 0 Falling Edge

0x0053

CP0FIF (CPT0CN.4)

ECP0F
(EIE1.4)

PCP0F
(EIP1.4)

Comparator 0 Rising Edge

0x005B

CP0RIF (CPT0CN.5)

ECP0R
(EIE1.5)

PCP0R
(EIP1.5)

Comparator 1 Falling Edge

0x0063

CP1FIF (CPT1CN.4)

ECP1F
(EIE1.6)

PCP1F
(EIP1.6)

Comparator 1 Rising Edge

0x006B

CP1RIF (CPT1CN.5)

ECP1R
(EIE1.7)

PCP1F
(EIP1.7)

Timer 3

0x0073

TF3 (TMR3CN.7)
EXF3 (TMR3CN.6)

ET3
(EIE2.0)

PT3
(EIP2.0)

ADC0 End of Conversion

0x007B

AD0INT (ADC0CN.5)

EADC0
(EIE2.1)

PADC0
(EIP2.1)

Timer 4

0x0083

TF4 (TMR4CN.7)
EXF4 (TMR4CN.7)

ET4
(EIE2.2)

PT4
(EIP2.2)

ADC2 Window Comparator

0x008B

AD2WINT
(ADC2CN.0)

EWADC2
(EIE2.3)

PWADC2
(EIP2.3)

ADC2 End of Conversion

0x0093

AD2INT (ADC2CN.5)

EADC2
(EIE2.4)

PADC2
(EIP2.4)

RESERVED

0x009B

N/A

N/A N/A

N/A

UART1

0x00A3

RI1 (SCON1.0)
TI1 (SCON1.1)

ES1
(EIE2.6)

PS1
(EIP2.6)

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12.7.3. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter-
rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each
interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority
is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If
both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.4.

12.7.4. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:
1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. Additional clock cycles
will be required if a cache miss occurs. If an interrupt is pending when a RETI is executed, a single instruction is exe-
cuted before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an inter-
rupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) is when the CPU is
performing an RETIinstruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the
CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.

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12.7.5. Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).

Figure 12.21. IE: Interrupt Enable

Bit7:

EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.

Bit6:

IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.

Bit5:

ET2: Enabler Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable Timer 2 interrupt.

Bit4:

ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.

Bit3:

ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable Timer 1 interrupt.
1: Enable Timer 1 interrupt.

Bit2:

EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable External Interrupt 1.
1: Enable External Interrupt 1.

Bit1:

ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable Timer 0 interrupts.
1: Enable Timer 0 interrupts.

Bit0:

EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable External Interrupt 0.
1: Enable External Interrupt 0.

R/W

Reset Value

IEGF0

ET2

ES0

ET1

EX1

ET0

EX0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xA8
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Figure 12.22. IP: Interrupt Priority

Bits7-6:

UNUSED. Read = 11b, Write = don't care.

Bit5:

PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority.
1: Timer 2 interrupt set to high priority.

Bit4:

PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority.
1: UART0 interrupts set to high priority.

Bit3:

PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority.
1: Timer 1 interrupts set to high priority.

Bit2:

PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority.
1: External Interrupt 1 set to high priority.

Bit1:

PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority.
1: Timer 0 interrupt set to high priority.

Bit0:

PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority.
1: External Interrupt 0 set to high priority.

R/W

Reset Value

PT2

PS0

PT1

PX1

PT0

PX0

11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xB8
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Figure 12.23. EIE1: Extended Interrupt Enable 1

Bit7:

ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt.
This bit sets the masking of the CP1 rising edge interrupt.
0: Disable CP1 rising edge interrupts.
1: Enable CP1 rising edge interrupts.

Bit6:

ECP1F: Enable Comparator1 (CP1) Falling Edge Interrupt.
This bit sets the masking of the CP1 falling edge interrupt.
0: Disable CP1 falling edge interrupts.
1: Enable CP1 falling edge interrupts.

Bit5:

ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt.
This bit sets the masking of the CP0 rising edge interrupt.
0: Disable CP0 rising edge interrupts.
1: Enable CP0 rising edge interrupts.

Bit4:

ECP0F: Enable Comparator0 (CP0) Falling Edge Interrupt.
This bit sets the masking of the CP0 falling edge interrupt.
0: Disable CP0 falling edge interrupts.
1: Enable CP0 falling edge interrupts.

Bit3:

EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable PCA0 interrupts.
1: Enable PCA0 interrupts.

Bit2:

EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable ADC0 Window Comparison Interrupt.

Bit1:

ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable SMBus interrupts.
1: Enable SMBus interrupts.

Bit0:

ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable SPI0 interrupts.
1: Enable SPI0 interrupts.

R/W

Reset Value

ECP1R

ECP1F

ECP0R

ECP0F

EPCA0

EWADC0

ESMB0

ESPI0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xE6
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Figure 12.24. EIE2: Extended Interrupt Enable 2

Bit7:

UNUSED. Read = 0b, Write = don't care.

Bit6:

ES1: Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupts.
1: Enable UART1 interrupts.

Bit5:

UNUSED. Read = 0b, Write = don't care.

Bit4:

EADC2: Enable ADC2 End Of Conversion Interrupt.
This bit sets the masking of the ADC2 End of Conversion interrupt.
0: Disable ADC2 End of Conversion interrupts.
1: Enable ADC2 End of Conversion Interrupts.

Bit3:

EWADC2: Enable Window Comparison ADC2 Interrupt.
This bit sets the masking of ADC2 Window Comparison interrupt.
0: Disable ADC2 Window Comparison Interrupts.
1: Enable ADC2 Window Comparison Interrupts.

Bit2:

ET4: Enable Timer 4 Interrupt
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4 interrupts.
1: Enable Timer 4 interrupts.

Bit1:

EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 End of Conversion Interrupts.
1: Enable ADC0 End of Conversion Interrupts.

Bit0:

ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable Timer 3 interrupts.

R/W

Reset Value

ES1

EADC2

EWADC2

ET4

EADC0

ET3

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xE7
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Figure 12.25. EIP1: Extended Interrupt Priority 1

Bit7:

PCP1R: Comparator1 (CP1) Rising Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 rising interrupt set to low priority.
1: CP1 rising interrupt set to high priority.

Bit6:

PCP1F: Comparator1 (CP1) Falling Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 falling interrupt set to low priority.
1: CP1 falling interrupt set to high priority.

Bit5:

PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 rising interrupt set to low priority.
1: CP0 rising interrupt set to high priority.

Bit4:

PCP0F: Comparator0 (CP0) Falling Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 falling interrupt set to low priority.
1: CP0 falling interrupt set to high priority.

Bit3:

PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority.
1: PCA0 interrupt set to high priority.

Bit2:

PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority.
1: ADC0 Window interrupt set to high priority.

Bit1:

PSMB0: System Management Bus (SMBus0) Interrupt Priority Control.
This bit sets the priority of the SMBus0 interrupt.
0: SMBus interrupt set to low priority.
1: SMBus interrupt set to high priority.

Bit0:

PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority.
1: SPI0 interrupt set to high priority.

R/W

Reset Value

PCP1R

PCP1F

PCP0R

PCP0F

PPCA0

PWADC0

PSMB0

PSPI0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xF6
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Figure 12.26. EIP2: Extended Interrupt Priority 2

Bit7:

UNUSED. Read = 0b, Write = don't care.

Bit6:

ES1: UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority.
1: UART1 interrupt set to high priority.

Bit5:

UNUSED. Read = 0b, Write = don't care.

Bit4:

PADC2: ADC2 End Of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC2 End of Conversion interrupt.
0: ADC2 End of Conversion interrupt set to low priority.
1: ADC2 End of Conversion interrupt set to high priority.

Bit3:

PWADC2: ADC2 Window Compare Interrupt Priority Control.
This bit sets the priority of the ADC2 Window Compare interrupt.
0: ADC2 Window Compare interrupt set to low priority.
1: ADC2 Window Compare interrupt set to high priority.

Bit2:

PT4: Timer 4 Interrupt Priority Control.
This bit sets the priority of the Timer 4 interrupt.
0: Timer 4 interrupt set to low priority.
1: Timer 4 interrupt set to high priority.

Bit1:

PADC0: ADC0 End of Conversion Interrupt Priority Control.
This bit sets the priority of the ADC0 End of Conversion Interrupt.
0: ADC0 End of Conversion interrupt set to low priority.
1: ADC0 End of Conversion interrupt set to high priority.

Bit0:

PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupts.
0: Timer 3 interrupt set to low priority.
1: Timer 3 interrupt set to high priority.

R/W

Reset Value

PS1

PADC2

PWADC2

PT4

PADC0

PT3

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xF7
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12.8.

Power Management Modes

The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU
while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and
timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in
Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in
active mode before entering Idle. Stop mode consumes the least power. Figure 12.27 describes the Power Control
Register (PCON) used to control the CIP-51's power management modes.

Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog periph-
eral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or serial buses,
draw little power whenever they are not in use. Turning off the Flash memory saves power, similar to entering Idle
mode. Turning off the oscillator saves even more power, but requires a reset to restart the MCU.

12.8.1. Idle Mode

Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes. All internal registers and memory maintain their original data. All analog and
digital peripherals can remain active during Idle mode.

Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume operation. The pending interrupt
will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the instruction
immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal or external
reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.

If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This fea-
ture protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON
register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle mode if the
WDT was initially configured to allow this operation. This provides the opportunity for additional power savings,
allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system.
Refer to

Section 14

for more information on the use and configuration of the WDT.

12.8.2. Stop Mode

Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital peripher-
als. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can only be ter-
minated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and begins program
execution at address 0x0000.

If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing
Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD timeout of 100 µs.

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13.

MULTIPLY AND ACCUMULATE (MAC0)

13.1.

Special Function Registers

There are thirteen Special Function Register (SFR) locations associated with MAC0. Two of these registers are
related to configuration and operation, while the other eleven are used to store multi-byte input and output data for
MAC0. The Configuration register MAC0CF (Figure 13.8) is used to configure and control MAC0. The Status reg-
ister MAC0STA (Figure 13.9) contains flags to indicate overflow conditions, as well as zero and negative results. The
16-bit MAC0A (MAC0AH:MAC0AL) and MAC0B (MAC0BH:MAC0BL) registers are used as inputs to the multi-
plier. The MAC0 Accumulator register is 40 bits long, and consists of five SFRs: MAC0OVR, MAC0ACC3,
MAC0ACC2, MAC0ACC1, and MAC0ACC0. The primary results of a MAC0 operation are stored in the Accumu-
lator registers. If they are needed, the rounded results are stored in the 16-bit Rounding Register MAC0RND
(MAC0RNDH:MAC0RNDL).

MAC0CF

MAC

SAT

MAC

MAC0STA

MAC

16 x 16 Multiply

MAC0RNDH

MAC0RNDL

MAC0 Rounding Register

MAC0OVR

MAC0ACC3

MAC0ACC2

MAC0ACC1

MAC0ACC0

MAC0 Accumulator

40 bitAdd

MAC0MS

Rounding Engine

1 bitShift

MAC0FM

Flag Logic

MAC0BH

MAC0BL

MAC0 B Register

MAC0AH

MAC0AL

MAC0 A Register

Figure 13.1. MAC0 Block Diagram

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13.2.

Integer and Fractional Math

MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed frac-
tional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to `0', the inputs are treated as 16-bit, 2's comple-
ment, integer values. After the operation, the accumulator will contain a 40-bit, 2's complement, integer value.
Figure 13.2 shows how integers are stored in the SFRs.

When the MAC0FM bit is set to `1', the inputs are treated at 16-bit, 2's complement, fractional values. The decimal
point is located between bits 15 and 14 of the data word. After the operation, the accumulator will contain a 40-bit,
2's complement, fractional value, with the decimal point located between bits 31 and 30. Figure 13.3 shows how
fractional numbers are stored in the SFRs.

-(2

)

-(2

)

High Byte

Low Byte

MAC0OVR

MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0

MAC0A and MAC0B BitWeighting

MAC0 Accumulator Bit Weighting

Figure 13.2. Integer Mode Data Representation

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

-(2

)

-1

-30

-31

-29

-2

-28

-3

-27

High Byte

Low Byte

MAC0OVR

MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0

MAC0A, and MAC0B BitWeighting

MAC0 Accumulator Bit Weighting

MAC0RND BitWeighting

* The MAC0RND register contains the 16 LSBs of a two's complement number. The MAC0N Flag can be
used to determine the sign of the MAC0RND register.

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-11

-12

-13

-14

-15

High Byte

Low Byte

* -2

Figure 13.3. Fractional Mode Data Representation

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13.3.

Operating in Multiply and Accumulate Mode

MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to `0'.
When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A and MAC0B
registers, and adds the result to the contents of the 40-bit MAC0 accumulator. Figure 13.4 shows the MAC0 pipeline.
There are three stages in the pipeline, each of which takes exactly one SYSCLK cycle to complete. The MAC opera-
tion is initiated with a write to the MAC0BL register. After the MAC0BL register is written, MAC0A and MAC0B
are multiplied on the first SYSCLK cycle. During the second stage of the MAC0 pipeline, the results of the multipli-
cation are added to the current accumulator contents, and the result of the addition is stored in the MAC0 accumula-
tor. The status flags in the MAC0STA register are set after the end of the second pipeline stage. During the second
stage of the pipeline, the next multiplication can be initiated by writing to the MAC0BL register, if it is desired. The
rounded (and optionally, saturated) result is available in the MAC0RNDH and MAC0RNDL registers at the end of
the third pipeline stage. If the MAC0CA bit (MAC0CF.3) is set to `1' when the MAC operation is initiated, the accu-
mulator and all MAC0STA flags will be cleared to zero during the first pipeline stage (before the multiplication
results are added).

13.4.

Operating in Multiply Only Mode

MAC0 operates in Multiply Only mode when the MAC0MS bit (MAC0CF.0) is set to `1'. Multiply Only mode is
identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of zero before
being stored in the MAC0 accumulator (i.e. it overwrites the current accumulator contents). The result of the multipli-
cation is available in the MAC0 accumulator registers at the end of the second MAC0 pipeline stage (two SYSCLKs
after writing to MAC0BL). As in MAC mode, the rounded result is available in the MAC0 Rounding Registers after
the third pipeline stage. Note that in Multiply Only mode, the MAC0HO flag is not affected.

13.5.

Accumulator Shift Operations

MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accumulator left
or right by one bit. The accumulator shift is initiated by writing a `1' to the MAC0SC bit (MAC0CF.5), and takes one
SYSCLK cycle (the rounded result is available in the MAC0 Rounding Registers after a second SYSCLK cycle). The
direction of the arithmetic shift is controlled by the MAC0SD bit (MAC0CF.4). When this bit is cleared to `0', the
MAC0 accumulator will shift left. When the MAC0SD bit is set to `1', the MAC0 accumulator will shift right. Right-
shift operations are sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register
are not affected by shift operations.

Multiply

Add

Round

Multiply

Add

Round

Write

MAC0BL

Write

MAC0BL

MAC0 Operation

Begins

NextMAC0

Operation May

Be Initiated

Here

Accumulator

Results Available

Rounded Results

Available

Figure 13.4. MAC0 Pipeline

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13.6.

Rounding and Saturation

A Rounding Engine is included, which can be used to provide a rounded result when operating on fractional numbers.
MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31-16 of the accumulator, as shown in
Table 13.1. Rounding occurs during the third stage of the MAC0 pipeline, after any shift operation, or on a write to
the LSB of the accumulator. The rounded results are stored in the rounding registers: MAC0RNDH (Figure 13.19)
and MAC0RNDL (Figure 13.20). The accumulator registers are not affected by the rounding engine. Although
rounding is primarily used for fractional data, the data in the rounding registers is updated in the same way when
operating in integer mode.

The rounding engine can also be used to saturate the results stored in the rounding registers. If the MAC0SAT bit is
set to `1' and the rounding register overflows, the rounding registers will saturate. When a positive overflow occurs,
the rounding registers will show a value of 0x7FFF when saturated. For a negative overflow, the rounding registers
will show a value of 0x8000 when saturated. If the MAC0SAT bit is cleared to `0', the rounding registers will not sat-
urate.

13.7.

Usage Examples

This section details some software examples for using MAC0. Figure 13.5 shows a series of two MAC operations
using fractional numbers. Figure 13.6 shows a single operation in Multiply Only mode with integer numbers. The last
example, shown in Figure 13.7, demonstrates how the left-shift and right-shift operations can be used to modify the
accumulator. All of the examples assume that all of the flags in the MAC0STA register are initially set to `0'.

Table 13.1. MAC0 Rounding (MAC0SAT = 0)

Accumulator Bits 15-0
(MAC0ACC1:MAC0ACC0)

Accumulator Bits 31-16
(MAC0ACC3:MAC0ACC2)

Rounding
Direction

Rounded Results
(MAC0RNDH:MAC0RNDL)

Greater Than 0x8000

Anything

(MAC0ACC3:MAC0ACC2) + 1

Less Than 0x8000

Anything

Down

(MAC0ACC3:MAC0ACC2)

Equal To 0x8000

Odd (LSB = 1)

(MAC0ACC3:MAC0ACC2) + 1

Equal To 0x8000

Even (LSB = 0)

Down

(MAC0ACC3:MAC0ACC2)

Figure 13.5. Multiply and Accumulate Example

The example below implements the equation:

MOV

MAC0CF, #0Ah

; Set to Clear Accumulator, Use fractional numbers

MOV

MAC0AH, #40h

; Load MAC0A register with 4000 hex = 0.5 decimal

MOV

MAC0AL, #00h

MOV

MAC0BH, #20h

; Load MAC0B register with 2000 hex = 0.25 decimal

MOV

MAC0BL, #00h

; This line initiates the first MAC operation

MOV

MAC0BH, #E0h

; Load MAC0B register with E000 hex = -0.25 decimal

MOV

MAC0BL, #00h

; This line initiates the second MAC operation

NOP

; After this instruction, the Accumulator should be equal to 0,

; and the MAC0STA register should be 0x04, indicating a zero

NOP

; After this instruction, the Rounding register is updated

0.5

0.25

(

)

0.5

0.25

(

)

0.125

0.0

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Figure 13.6. Multiply Only Example

The example below implements the equation:

MOV

MAC0CF, #01h

; Use integer numbers, and multiply only mode (add to zero)

MOV

MAC0AH, #12h

; Load MAC0A register with 1234 hex = 4660 decimal

MOV

MAC0AL, #34h

MOV

MAC0BH, #FEh

; Load MAC0B register with FEDC hex = -292 decimal

MOV

MAC0BL, #DCh

; This line initiates the Multiply operation

NOP

; After this instruction, the Accumulator should be equal to

; FFFFEB3CB0 hex = -1360720 decimal. The MAC0STA register should

; be 0x01, indicating a negative result.

NOP

; After this instruction, the Rounding register is updated

4660

292

1360720

Figure 13.7. MAC0 Accumulator Shift Example

The example below shifts the MAC0 accumulator left one bit, and then right two bits:

MOV

MAC0OVR, #40h

; The next few instructions load the accumulator with the value

MOV

MAC0ACC3, #88h

; 4088442211 Hex.

MOV

MAC0ACC2, #44h

MOV

MAC0ACC1, #22h

MOV

MAC0ACC0, #11h

MOV

MAC0CF, #20h

; Initiate a Left-shift

NOP

; After this instruction, the accumulator should be 0x8110884422

NOP

; The rounding register is updated after this instruction

MOV

MAC0CF, #30h

; Initiate a Right-shift

MOV

MAC0CF, #30h

; Initiate a second Right-shift

NOP

; After this instruction, the accumulator should be 0xE044221108

NOP

; The rounding register is updated after this instruction

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Figure 13.8. MAC0CF: MAC0 Configuration Register

Bits 7-6:

UNUSED: Read = 00b, Write = don't care.

Bit 5:

MAC0SC: Accumulator Shift Control.
When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK cycle.
The direction of the shift (left or right) is controlled by the MAC0RS bit.
This bit is cleared to `0' by hardware when the shift is complete.

Bit 4:

MAC0SD: Accumulator Shift Direction.
This bit controls the direction of the accumulator shift activated by the MAC0SC bit.
0: MAC0 Accumulator will be shifted left.
1: MAC0 Accumulator will be shifted right.

Bit 3:

MAC0CA: Clear Accumulator.
This bit is used to reset MAC0 before the next operation.
When set to `1', the MAC0 Accumulator will be cleared to zero and the MAC0 Status register will be
reset during the next SYSCLK cycle.
This bit will be cleared to `0' by hardware when the reset is complete.

Bit 2:

MAC0SAT: Saturate Rounding Register.
This bit controls whether the Rounding Register will saturate. If this bit is set and a Soft Overflow
occurs, the Rounding Register will saturate. This bit does not affect the operation of the MAC0 Accu-
mulator. See Section 13.6 for more details about rounding and saturation.
0: Rounding Register will not saturate.
1: Rounding Register will saturate.

Bit 1:

MAC0FM: Fractional Mode.
This bit selects between Integer Mode and Fractional Mode for MAC0 operations.
0: MAC0 operates in Integer Mode.
1: MAC0 operates in Fractional Mode.

Bit 0:

MAC0MS: Mode Select
This bit selects between MAC Mode and Multiply Only Mode.
0: MAC (Multiply and Accumulate) Mode.
1: Multiply Only Mode.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

R/W

Reset Value

MAC0SC

MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xC3

SFR Page: 3

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Figure 13.9. MAC0STA: MAC0 Status Register

Bits 7-4:

UNUSED: Read = 0000b, Write = don't care.

Bit 3:

MAC0HO: Hard Overflow Flag.
This bit is set to `1' whenever an overflow out of the MAC0OVR register occurs during a MAC oper-
ation (i.e. when MAC0OVR changes from 0x7F to 0x80 or from 0x80 to 0x7F).
The hard overflow flag must be cleared in software by directly writing it to `0', or by resetting the
MAC logic using the MAC0CA bit in register MAC0CF.

Bit 2:

MAC0Z: Zero Flag.
This bit is set to `1' if a MAC0 operation results in an Accumulator value of zero. If the result is non-
zero, this bit will be cleared to `0'.

Bit 1:

MAC0SO: Soft Overflow Flag.
This bit is set to `1' when a MAC operation causes an overflow into the MAC0OVR register (i.e.
when the MAC0OVR register is not equal to 0x00 or 0xFF). If the MAC0OVR register is equal to
0x00 or 0xFF after a MAC operation, this bit is cleared to `0'.

Bit 0:

MAC0N: Negative Flag.
If the MAC Accumulator result is negative, this bit will be set to `1'. If the result is positive or zero,
this flag will be cleared to `0'.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

R/W

Reset Value

MAC0HO

MAC0Z

MAC0SO

MAC0N

00000100

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address: 0xC0

SFR Page: 3

Figure 13.10. MAC0AH: MAC0 A High Byte Register

Bits 7-0:

High Byte (bits 15-8) of MAC0 A Register.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xC2

SFR Page: 3

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C8051F124/5/6/7

Figure 13.11. MAC0AL: MAC0 A Low Byte Register

Bits 7-0:

Low Byte (bits 7-0) of MAC0 A Register.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xC1

SFR Page: 3

Figure 13.12. MAC0BH: MAC0 B High Byte Register

Bits 7-0:

High Byte (bits 15-8) of MAC0 B Register.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x92

SFR Page: 3

Figure 13.13. MAC0BL: MAC0 B Low Byte Register

Bits 7-0:

Low Byte (bits 7-0) of MAC0 B Register.
A write to this register initiates a Multiply or Multiply and Accumulate operation.

Note: The contents of this register should not be changed by software during the first MAC0 pipeline stage.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x91

SFR Page: 3

Figure 13.14. MAC0ACC3: MAC0 Accumulator Byte 3 Register

Bits 7-0:

Byte 3 (bits 31-24) of MAC0 Accumulator.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x96

SFR Page: 3

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Figure 13.15. MAC0ACC2: MAC0 Accumulator Byte 2 Register

Bits 7-0:

Byte 2 (bits 23-16) of MAC0 Accumulator.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x95

SFR Page: 3

Figure 13.16. MAC0ACC1: MAC0 Accumulator Byte 1 Register

Bits 7-0:

Byte 1 (bits 15-8) of MAC0 Accumulator.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x94

SFR Page: 3

Figure 13.17. MAC0ACC0: MAC0 Accumulator Byte 0 Register

Bits 7-0:

Byte 0 (bits 7-0) of MAC0 Accumulator.

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x93

SFR Page: 3

Figure 13.18. MAC0OVR: MAC0 Accumulator Overflow Register

Bits 7-0:

MAC0 Accumulator Overflow Bits (bits 39-32).

Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0x97

SFR Page: 3

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14.

RESET SOURCES

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state,
the following occur:

CIP-51 halts program execution.

Special Function Registers (SFRs) are initialized to their defined reset values.

External port pins are forced to a known configuration.

Interrupts and timers are disabled.

All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal data mem-
ory are unaffected during a reset; any previously stored data is preserved. However, since the stack pointer SFR is
reset, the stack is effectively lost even though the data on the stack are not altered.

The I/O port latches are reset to 0xFF (all logic 1's), activating internal weak pull-ups during and after the reset. For
VDD Monitor resets, the /RST pin is driven low until the end of the VDD reset timeout.

On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal oscillator
running at its lowest frequency. Refer to Section "

15. OSCILLATORS

" on page

173

for information on selecting

and configuring the system clock source. The Watchdog Timer is enabled using its longest timeout interval (see Sec-
tion "

14.7. Watchdog Timer Reset

" on page

169

). Once the system clock source is stable, program execution begins

at location 0x0000.

There are seven sources for putting the MCU into the reset state: power-on, power-fail, external /RST pin, external
CNVSTR0 signal, software command, Comparator0, Missing Clock Detector, and Watchdog Timer. Each reset
source is described in the following sections.

WDT

XTAL1

XTAL2

OSC

Internal

Clock

Generator

System
Clock

CIP-51

Microcontroller

Core

Missing

Clock

Detector

(one-

shot)

Str

Software Reset

Extended Interrupt

Handler

Clock Select

/RST

+
-

VDD

Supply

Reset

Timeout

(wired-OR)

System Reset

Supply
Monitor

PRE

Reset
Funnel

+
-

CP0+

Comparator0

CP0-

(Port

I/O)

Crossbar

CNVSTR

(CNVSTR

reset

enable)

(CP0
reset

enable)

l
e

MCD

l
e

PLL

Circuitry

Figure 14.1. Reset Sources

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C8051F124/5/6/7

14.1.

Power-on Reset

The C8051F120/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset state until
VDD rises above the V

RST

level during power-up. See Figure 14.2 for timing diagram, and refer to Table 14.1 for the

Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end of the
100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize. The VDD Monitor reset is enabled and
disabled using the external VDD monitor enable pin (MONEN).

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset flags
in the RSTSRC Register are indeterminate. PORSF is cleared by all other resets. Since all resets cause program exe-
cution to begin at the same location (0x0000) software can read the PORSF flag to determine if a power-up was the
cause of reset. The contents of internal data memory should be assumed to be undefined after a power-on reset.

14.2.

Power-fail Reset

When a power-down transition or power irregularity causes VDD to drop below V

RST

, the power supply monitor will

drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level above VRST, the CIP-51
will leave the reset state in the same manner as that for the power-on reset (see Figure 14.2). Note that even though
internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped
below the level required for data retention. If the PORSF flag is set to logic 1, the data may no longer be valid.

14.3.

External Reset

The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting the /RST
pin low will cause the MCU to enter the reset state. It may be desirable to provide an external pull-up and/or decou-
pling of the /RST pin to avoid erroneous noise-induced resets. The MCU will remain in reset until at least 12 clock
cycles after the active-low /RST signal is removed. The PINRSF flag (RSTSRC.0) is set on exit from an external
reset.

VDD Monitor Reset

Power-On Reset

/RST

l
ts

1.0

2.0

Logic HIGH

Logic LOW

100ms

2.70

2.55

RST

Figure 14.2. Reset Timing

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Preliminary

C8051F120/1/2/3
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14.4.

Missing Clock Detector Reset

The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the system
clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a Missing Clock Detector
reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this bit reads `0'.
The state of the /RST pin is unaffected by this reset. Setting the MCDRSF bit, RSTSRC.2 (see Section
"

15. OSCILLATORS

" on page

173

) enables the Missing Clock Detector.

14.5.

Comparator0 Reset

Comparator0 can be configured as a reset input by writing a `1' to the C0RSEF flag (RSTSRC.5). Comparator0
should be enabled using CPT0CN.7 (see Section "

11. COMPARATORS

" on page

111

) prior to writing to C0RSEF

to prevent any turn-on chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low:
if the non-inverting input voltage (CP0+ pin) is less than the inverting input voltage (CP0- pin), the MCU is put into
the reset state. After a Comparator0 Reset, the C0RSEF flag (RSTSRC.5) will read `1' signifying Comparator0 as the
reset source; otherwise, this bit reads `0'. The state of the /RST pin is unaffected by this reset.

14.6.

External CNVSTR0 Pin Reset

The external CNVSTR0 signal can be configured as a reset input by writing a `1' to the CNVRSEF flag (RSTSRC.6).
The CNVSTR0 signal can appear on any of the P0, P1, P2 or P3 I/O pins as described in Section "

19.1. Ports 0

through 3 and the Priority Crossbar Decoder

" on page

217

. Note that the Crossbar must be configured for the

CNVSTR0 signal to be routed to the appropriate Port I/O. The Crossbar should be configured and enabled before the
CNVRSEF is set. When configured as a reset, CNVSTR0 is active-low and level sensitive. CNVSTR0 cannot be
used to start ADC0 conversions when it is configured as a reset source. After a CNVSTR0 reset, the CNVRSEF flag
(RSTSRC.6) will read `1' signifying CNVSTR0 as the reset source; otherwise, this bit reads `0'. The state of the

RST

pin is unaffected by this reset.

14.7.

Watchdog Timer Reset

The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow will
force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application software before
overflow. If the system experiences a software or hardware malfunction preventing the software from restarting the
WDT, the WDT will overflow and cause a reset. This should prevent the system from running out of control.

Following a reset the WDT is automatically enabled and running with the default maximum time interval. If desired
the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the WDT
cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset.

The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period
between specific writes to its control register. If this period exceeds the programmed limit, a WDT reset is generated.
The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog
features are controlled via the Watchdog Timer Control Register (WDTCN) shown in Figure 14.3.

14.7.1. Enable/Reset WDT

The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's application soft-
ware should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. The WDT
is enabled and reset as a result of any system reset.

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14.7.2. Disable WDT

Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates
disabling the WDT:

CLR

; disable all interrupts

MOV

WDTCN,#0DEh

; disable software watchdog timer

MOV

WDTCN,#0ADh

SETB

; re-enable interrupts

The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored.
This means that the prefetch engine should be enabled and interrupts should be disabled during this procedure to
avoid any delay between the two writes.

14.7.3. Disable WDT Lockout

Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the
next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use the
watchdog should write 0xFF to WDTCN in the initialization code.

14.7.4. Setting WDT Interval

WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation:

; where T

sysclk

is the system clock period.

For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be logic 0 when
setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b after a system
reset.

WDTCN 2

[

]

sysclk

Bits7-0:

WDT Control
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature.

Bit4:

Watchdog Status Bit (when Read)
Reading the WDTCN.[4] bit indicates the Watchdog Timer Status.
0: WDT is inactive
1: WDT is active

Bits2-0:

Watchdog Timeout Interval Bits
The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must
be set to 0.

R/W

Reset Value

xxxxx111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xFF
All Pages

Figure 14.3. WDTCN: Watchdog Timer Control Register

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Preliminary

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Figure 14.4. RSTSRC: Reset Source Register

Bit7:

Reserved.

Bit6:

CNVRSEF: Convert Start 0 Reset Source Enable and Flag
Write:

0: CNVSTR0 is not a reset source.
1: CNVSTR0 is a reset source (active low).

Read:

0: Source of prior reset was not CNVSTR0.
1: Source of prior reset was CNVSTR0.

Bit5:

C0RSEF: Comparator0 Reset Enable and Flag.
Write:

0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).

Read:

0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.

Bit4:

SWRSF: Software Reset Force and Flag.
Write:

0: No effect.
1: Forces an internal reset. /RST pin is not effected.

Read:

0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.

Bit3:

WDTRSF: Watchdog Timer Reset Flag.

0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.

Bit2:

MCDRSF: Missing Clock Detector Flag.
Write:

0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected.

Read:

0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.

Bit1:

PORSF: Power-On Reset Flag.
Write: If the VDD monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this
bit can be written to select or de-select the VDD monitor as a reset source.
0: De-select the VDD monitor as a reset source.
1: Select the VDD monitor as a reset source.
Important: At power-on, the VDD monitor is enabled/disabled using the external VDD monitor
enable pin (MONEN). The PORSF bit does not disable or enable the VDD monitor circuit. It
simply selects the VDD monitor as a reset source.
Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on reset or a
VDD monitor reset. In either case, data memory should be considered indeterminate following the
reset.
0: Source of last reset was not a power-on or VDD monitor reset.
1: Source of last reset was a power-on or VDD monitor reset.
Note: When this flag is read as '1', all other reset flags are indeterminate.

Bit0:

PINRSF: HW Pin Reset Flag.
Write:

0: No effect.
1: Forces a Power-On Reset. /RST is driven low.

Read:

0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.

R/W

Reset Value

CNVRSEF

C0RSEF

SWRSEF

WDTRSF

MCDRSF

PORSF

PINRSF

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xEF
0

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

15.

OSCILLATORS

C8051F120/1/2/3/4/5/6/7 devices include a programmable internal oscillator and an external oscillator drive circuit.
The internal oscillator can be enabled, disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 15.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or the on-chip
phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 15.1 on page 173.

15.1.

Programmable Internal Oscillator

All C8051F12x devices include a programmable internal oscillator that defaults as the system clock after a system
reset. The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 15.2. OSCICL is
factory calibrated to obtain a 24.5 MHz frequency.

Electrical specifications for the precision internal oscillator are given in Table 15.1. Note that the system clock may
be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register
OSCICN.

Table 15.1. Oscillator Electrical Characteristics

-40°C to +85°C unless otherwise specified

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Calibrated Internal Oscillator
Frequency

24.5

MHz

Internal Oscillator Supply Current
(from VDD)

OSCICN.7 = 1

400

µA

External Clock Frequency

MHz

XCH

(External Clock High Time)

XCL

(External Clock Low Time)

OSC

Calibrated

Internal

Oscillator

Input

Circuit

SYSCLK

OSCICL

OSCICN

IOS

CN1

CN0

XTAL1

XTAL2

Option 2

VDD

XTAL1

Option 1

Option 4

XTAL1

OSCXCN

XFC

CLKSEL

KDIV

PLL

Option 3

XTAL1

XTAL2

AGND

AV+

Figure 15.1. Oscillator Diagram

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C8051F120/1/2/3
C8051F124/5/6/7

Figure 15.2. OSCICL: Internal Oscillator Calibration Register

Bits 7-0:

OSCICL: Internal Oscillator Calibration Register.
This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal
oscillator base frequency. The reset value is factory calibrated to generate an internal oscillator fre-
quency of 24.5 MHz.

R/W

Reset Value

Variable

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8B
F

Figure 15.3. OSCICN: Internal Oscillator Control Register

Bit 7:

IOSCEN: Internal Oscillator Enable Bit.
0: Internal Oscillator Disabled.
1: Internal Oscillator Enabled.

Bit 6:

IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator not running at programmed frequency.
1: Internal Oscillator running at programmed frequency.

Bits 5-2:

Reserved.

Bits 1-0:

IFCN1-0: Internal Oscillator Frequency Control Bits.
00: Internal Oscillator is divided by 8.
01: Internal Oscillator is divided by 4.
10: Internal Oscillator is divided by 2.
11: Internal Oscillator is divided by 1.

R/W

Reset Value

IOSCEN

IFRDY

IFCN1

IFCN0

11000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8A
F

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

15.2.

External Oscillator Drive Circuit

The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS
clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be
wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 15.1. In RC, capacitor, or CMOS clock
configuration, the clock source should be wired to the XTAL2 and/or XTAL1 pin(s) as shown in Option 2, 3, or 4 of
Figure 15.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits
(XFCN) must be selected appropriately (see Figure 15.5).

15.3.

System Clock Selection

The CLKSL1-0 bits in register CLKSEL select which oscillator source generates the system clock. CLKSL1-0 must
be set to `01' for the system clock to run from the external oscillator; however the external oscillator may still clock
certain peripherals, such as the timers and PCA, when the internal oscillator or the PLL is selected as the system
clock. The system clock may be switched on-the-fly between the internal and external oscillators or the PLL, so long
as the selected oscillator source is enabled and settled. The internal oscillator requires little start-up time, and may be
enabled and selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use as the system clock. The Crystal Valid Flag
(XTLVLD in register OSCXCN) is set to `1' by hardware when the external oscillator is settled. To avoid reading a
false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and
checking XTLVLD. RC and C modes typically require no startup time. The PLL also requires time to lock onto the
desired frequency, and the PLL Lock Flag (PLLLCK in register PLL0CN) is set to `1' by hardware once the PLL is
locked on the correct frequency.

Figure 15.4. CLKSEL: System Clock Selection Register

Bits 7-6:

Reserved.

Bits 5-4:

CLKDIV1-0: Output SYSCLK Divide Factor.
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See

Section "19. PORT INPUT/OUTPUT" on page 215

for more details about routing this output

to a port pin.

Bits 3-2:

Reserved.

Bits 1-0:

CLKSL1-0: System Clock Source Select Bits.
00: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the PLL.
11: Reserved.

R/W

Reset Value

CLKDIV1 CLKDIV0

CLKSL1

CLKSL0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x97
F

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C8051F120/1/2/3
C8051F124/5/6/7

Figure 15.5. OSCXCN: External Oscillator Control Register

Bit7:

XTLVLD: Crystal Oscillator Valid Flag.
(Valid only when XOSCMD = 11x.)
0: Crystal Oscillator is unused or not yet stable.
1: Crystal Oscillator is running and stable.

Bits6-4:

XOSCMD2-0: External Oscillator Mode Bits.
00x: External Oscillator circuit off.
010: External CMOS Clock Mode (External CMOS Clock input on XTAL1 pin).
011: External CMOS Clock Mode with divide by 2 stage (External CMOS Clock input on XTAL1
pin).
10x: RC/C Oscillator Mode with divide by 2 stage.
110: Crystal Oscillator Mode.
111: Crystal Oscillator Mode with divide by 2 stage.

Bit3:

RESERVED. Read = 0, Write = don't care.

Bits2-0:

XFCN2-0: External Oscillator Frequency Control Bits.
000-111: see table below:

CRYSTAL MODE (Circuit from Figure 15.1, Option 1; XOSCMD = 11x)

Choose XFCN value to match crystal frequency.

RC MODE (Circuit from Figure 15.1, Option 2; XOSCMD = 10x)

Choose XFCN value to match frequency range:

f = 1.23(10

) / (R * C), where

f = frequency of oscillation in MHz
C = capacitor value in pF
R = Pull-up resistor value in k

C MODE (Circuit from Figure 15.1, Option 3; XOSCMD = 10x)

Choose K Factor (KF) for the oscillation frequency desired:
f = KF / (C * VDD), where
f = frequency of oscillation in MHz
C = capacitor value on XTAL1, XTAL2 pins in pF

R/W

Reset Value

XTLVLD XOSCMD2 XOSCMD1 XOSCMD0

XFCN2

XFCN1

XFCN0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8C
F

XFCN

Crystal (XOSCMD = 11x)

RC (XOSCMD = 10x)

C (XOSCMD = 10x)

000

32kHz

25kHz

K Factor = 0.87

001

32kHz

< f 84kHz

25kHz

< f 50kHz

K Factor = 2.6

010

84kHz

< f 225kHz

50kHz

< f 100kHz

K Factor = 7.7

011

225kHz

< f 590kHz

100kHz

< f 200kHz

K Factor = 22

100

590kHz

< f 1.5MHz

200kHz

< f 400kHz

K Factor = 65

101

1.5MHz

< f 4MHz

400kHz

< f 800kHz

K Factor = 180

110

4MHz

< f 10MHz

800kHz

< f 1.6MHz

K Factor = 664

111

10MHz

< f 30MHz

1.6MHz

< f 3.2MHz

K Factor = 1590

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

15.4.

External Crystal Example

If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured
as shown in Figure 15.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from
the Crystal column of the table in Figure 15.5 (OSCXCN register). For example, an 11.0592 MHz crystal requires an
XFCN setting of 111b.

When the crystal oscillator is enabled, the oscillator amplitude detection circuit requires a settle time to achieve
proper bias. Waiting at least 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a pre-
mature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure is:

Step 1. Enable the external oscillator.
Step 2. Wait at least 1 ms.
Step 3. Poll for XTLVLD => `1'.
Step 4. Switch the system clock to the external oscillator.

Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal
should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and
shielded with ground plane from any other traces which could introduce noise or interference.

15.5.

External RC Example

If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in
Figure 15.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total
capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscil-
lator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the
desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 k

and C = 50 pF:

f = 1.23( 10

) / RC = 1.23 ( 10

) / [ 246 * 50 ] = 0.1 MHz = 100 kHz

Referring to the table in Figure 15.5, the required XFCN setting is 010.

15.6.

External Capacitor Example

If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 15.1,
Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance
may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Fre-
quency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of
oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF:

f = KF / ( C * VDD ) = KF / ( 50 * 3 )
f = KF / 150

If a frequency of roughly 50 kHz is desired, select the K Factor from the table in Figure 15.5 as KF = 7.7:

f = 7.7 / 150 = 0.051 MHz, or 51 kHz

Therefore, the XFCN value to use in this example is 010.

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C8051F120/1/2/3
C8051F124/5/6/7

15.7.

Phase-Locked Loop (PLL)

The C8051F12x Family include a Phase-Locked-Loop (PLL), which is used to multiply the internal oscillator or an
external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an out-
put frequency between 25 MHz and 100 MHz, from a divided reference frequency between 5 MHz and 30 MHz. A
block diagram of the PLL is shown in Figure 15.6.

15.7.1. PLL Input Clock and Pre-divider

The PLL circuitry can derive its reference clock from either the internal oscillator or an external clock source. The
PLLSRC bit (PLL0CN.2) controls which clock source is used for the reference clock (see Figure 15.7). If PLLSRC is
set to `0', the internal oscillator source is used. Note that the internal oscillator divide factor (as specified by bits
IFCN1-0 in register OSCICN) will also apply to this clock. When PLLSRC is set to `1', an external oscillator source
will be used. The external oscillator should be active and settled before it is selected as a reference clock for the PLL
circuit. The reference clock is divided down prior to the PLL circuit, according to the contents of the PLLM4-0 bits in
the PLL Pre-divider Register (PLL0DIV), shown in Figure 15.8.

15.7.2. PLL Multiplication and Output Clock

The PLL circuitry will multiply the divided reference clock by the multiplication factor stored in the PLL0MUL reg-
ister shown in Figure 15.9. To accomplish this, it uses a feedback loop consisting of a phase/frequency detector, a
loop filter, and a current-controlled oscillator (ICO). It is important to configure the loop filter and the ICO for the
correct frequency ranges. The PLLLP3-0 bits (PLL0FLT.3-0) should be set according to the divided reference clock
frequency. Likewise, the PLLICO1-0 bits (PLL0FLT.5-4) should be set according to the desired output frequency
range. Figure 15.10 describes the proper settings to use for the PLLLP3-0 and PLLICO1-0 bits. When the PLL is
locked and stable at the desired frequency, the PLLLCK bit (PLL0CN.5) will be set to a `1'. The resulting PLL fre-
quency will be set according to the equation:

Where "Reference Frequency" is the selected source clock frequency, PLLN is the PLL Multiplier, and PLLM is the
PLL Pre-divider.

PLL0DIV

LLM4

LLM3

LLM2

LLM1

LLM0

PLL0MUL

LLN

PLL0CN

LLLC

LLS

LLE

LLP

PLL0FLT

LLIC

LLLP

Internal

Oscillator

External

Oscillator

Phase /

Frequency

Detection

Loop Filter

Current

Controlled

Oscillator

PLL Clock

Output

Divided

Reference

Clock

Figure 15.6. PLL Block Diagram

PLL Frequency

Reference Frequency

PLLN

PLLM

----------------

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

15.7.3. Powering on and Initializing the PLL

To set up and use the PLL as the system clock after power-up of the device, the following procedure should be imple-
mented:

Step 1. Ensure that the reference clock to be used (internal or external) is running and stable.
Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL.
Step 3. Program the FLASH read timing bits, FLRT (FLSCL.5-4) to the appropriate value for the new clock

rate (see

Section "16. FLASH MEMORY" on page 185

Step 4. Enable power to the PLL by setting PLLPWR (PLL0CN.0) to `1'.
Step 5. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
Step 6. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided reference

frequency.

Step 7. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output frequency.
Step 8. Program the PLL0MUL register to the desired clock multiplication factor.
Step 9. Wait at least 5

µs, to provide a fast frequency lock.

Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to `1'.
Step 11. Poll PLLLCK (PLL0CN.4) until it changes from `0' to `1'.
Step 12. Switch the System Clock source to the PLL using the CLKSEL register.

If the PLL characteristics need to be changed when the PLL is already running, the following procedure should be
implemented:

Step 1. The system clock should first be switched to either the internal oscillator or an external clock source

that is running and stable, using the CLKSEL register.

Step 2. Ensure that the reference clock to be used for the new PLL setting (internal or external) is running

and stable.

Step 3. Set the PLLSRC bit (PLL0CN.2) to select the new clock source for the PLL.
Step 4. If moving to a faster frequency, program the FLASH read timing bits, FLRT (FLSCL.5-4) to the

appropriate value for the new clock rate (see

Section "16. FLASH MEMORY" on page 185

Step 5. Disable the PLL by setting PLLEN (PLL0CN.1) to `0'.
Step 6. Program the PLL0DIV register to produce the divided reference frequency to the PLL.
Step 7. Program the PLLLP3-0 bits (PLL0FLT.3-0) to the appropriate range for the divided reference

frequency.

Step 8. Program the PLLICO1-0 bits (PLL0FLT.5-4) to the appropriate range for the PLL output frequency.
Step 9. Program the PLL0MUL register to the desired clock multiplication factor.
Step 10. Enable the PLL by setting PLLEN (PLL0CN.1) to `1'.
Step 11. Poll PLLLCK (PLL0CN.4) until it changes from `0' to `1'.
Step 12. Switch the System Clock source to the PLL using the CLKSEL register.
Step 13. If moving to a slower frequency, program the FLASH read timing bits, FLRT (FLSCL.5-4) to the

appropriate value for the new clock rate (see

Section "16. FLASH MEMORY" on page 185

To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external clock source,
using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to `0'. Finally, the PLL can be
powered off, by setting PLLPWR (PLL0CN.0) to `0'. Note that the PLLEN and PLLPWR bits can be cleared at the
same time.

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C8051F120/1/2/3
C8051F124/5/6/7

Figure 15.7. PLL0CN: PLL Control Register

Bits 7-5:

UNUSED: Read = 000b; Write = don't care.

Bit 4:

PLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.

Bit 3:

RESERVED. Must write to `0'.

Bit 2:

PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.

Bit 1:

PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be `1'.

Bit 0:

PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.

R/W

Reset Value

PLLLCK

PLLSRC

PLLEN

PLLPWR

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x89
F

Figure 15.8. PLL0DIV: PLL Pre-divider Register

Bits 7-5:

UNUSED: Read = 000b; Write = don't care.

Bits 4-0:

PLLM4-0: PLL Reference Clock Pre-divider.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero value, the
reference clock will be divided by the value in PLLM4-0. When set to `00000b', the reference clock
will be divided by 32.

R/W

Reset Value

PLLM4

PLLM3

PLLM2

PLLM1

PLLM0

00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8D
F

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 15.9. PLL0MUL: PLL Clock Scaler Register

Bits 7-0:

PLLN7-0: PLL Multiplier.
These bits select the multiplication factor of the divided PLL reference clock. When set to any non-
zero value, the multiplication factor will be equal to the value in PLLN7-0. When set to `00000000b',
the multiplication factor will be equal to 256.

R/W

Reset Value

PLLN7

PLLN6

PLLN5

PLLN4

PLLN3

PLLN2

PLLN1

PLLN0

00000001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8E
F

Figure 15.10. PLL0FLT: PLL Filter Register

Bits 7-6:

UNUSED: Read = 00b; Write = don't care.

Bits 5-4:

PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Selection is based on the desired output frequency, according to the following table:

Bits 3-0:

PLLLP3-0: PLL Loop Filter Control Bits.
Selection is based on the divided PLL reference clock, according to the following table:

R/W

Reset Value

PLLICO1

PLLICO0

PLLLP3

PLLLP2

PLLLP1

PLLLP0

00110001

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8F
F

PLL Output Clock

PLLICO1-0

65 - 100 MHz

45 - 80 MHz

30 - 60 MHz

25 - 50 MHz

Divided PLL Reference Clock

PLLLP3-0

19 - 30 MHz

0001

12.2 - 19.5 MHz

0011

7.8 - 12.5 MHz

0111

5 - 8 MHz

1111

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C8051F120/1/2/3
C8051F124/5/6/7

16.

FLASH MEMORY

The C8051F12x family includes 128k + 256 bytes of on-chip, reprogrammable FLASH memory for program code
and non-volatile data storage. The FLASH memory can be programmed in-system through the JTAG interface, or by
software using the MOVX write instructions. Once cleared to logic 0, a FLASH bit must be erased to set it back to
logic 1. Bytes should be erased (set to 0xFF) before being reprogrammed. FLASH write and erase operations are
automatically timed by hardware for proper execution. During a FLASH erase or write, the FLBUSY bit in the
FLSTAT register is set to `1' (see Figure 17.8). During this time, instructions that are located in the prefetch buffer or
the branch target cache can be executed, but the processor will stall until the erase or write is completed if instruction
data must be fetched from FLASH memory. Interrupts that have been pre-loaded into the branch target cache can
also be serviced at this time, if the current code is also executing from the prefetch engine or cache memory. Any
interrupts that are not pre-loaded into cache, or that occur while the core is halted, will be held in a pending state dur-
ing the FLASH write/erase operation, and serviced in priority order once the FLASH operation has completed. Refer
to Table 16.1 for the electrical characteristics of the FLASH memory.

16.1.

Programming The Flash Memory

The simplest means of programming the FLASH memory is through the JTAG interface using programming tools
provided by Cygnal or a third party vendor. This is the only means for programming a non-initialized device. For
details on the JTAG commands to program FLASH memory, see

Section "26. JTAG (IEEE 1149.1)" on page 315

The FLASH memory can be programmed from software using the MOVX write instruction with the address and data
byte to be programmed provided as normal operands. Before writing to FLASH memory using MOVX, FLASH write
operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. This directs
the MOVX writes to FLASH memory instead of to XRAM, which is the default target. The PSWE bit remains set
until cleared by software. To avoid errant FLASH writes, it is recommended that interrupts be disabled while the
PSWE bit is logic 1.

FLASH memory is read using the MOVC instruction. MOVX reads are always directed to XRAM, regardless of the
state of PSWE.

The COBANK bits in the PSBANK register (Figure 12.3) determine which of the upper three FLASH banks are
mapped to the address range 0x08000 to 0x0FFFF for FLASH writes, reads and erases.

NOTE: To ensure the integrity of FLASH memory contents, it is strongly recommended that the on-chip VDD
monitor be enabled by connecting the VDD monitor enable pin (MONEN) to VDD in any system that writes
and/or erases FLASH memory from software. See "RESET SOURCES" on page 167 for more information.

A write to FLASH memory can clear bits but cannot set them; only an erase operation can set bits in FLASH. A byte
location to be programmed must be erased before a new value can be written.

16.1.1. Non-volatile Data Storage

The FLASH memory can be used for non-volatile data storage as well as program code. This allows data such as cal-
ibration coefficients to be calculated and stored at run time. Data is written and erased using the MOVX write instruc-
tion (as described in

Section 16.1.2

and

Section 16.1.3

) and read using the MOVC instruction. The COBANK bits in

register PSBANK (Figure 12.3) control which portion of the FLASH memory is targeted by writes and erases of
addresses above 0x07FFF.

Two additional 128-byte sectors (256 bytes total) of FLASH memory are included for non-volatile data storage. The
smaller sector size makes them particularly well suited as general purpose, non-volatile scratchpad memory. Even
though FLASH memory can be written a single byte at a time, an entire sector must be erased first. In order to change
a single byte of a multi-byte data set, the data must be moved to temporary storage. The 128-byte sector-size facili-

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tates updating data without wasting program memory or RAM space. The 128-byte sectors are double-mapped over
the 128k byte FLASH memory for MOVC reads and MOVX writes only; their addresses range from 0x00 to 0x7F
and from 0x80 to 0xFF (see Figure 16.2). To access the 128-byte sectors, the SFLE bit in PSCTL must be set to logic
1. Code execution from the 128-byte Scratchpad areas is not possible. The 128-byte sectors can be erased individu-
ally, or both at the same time. To erase both sectors simultaneously, the address 0x0400 should be targeted during the
erase operation with SFLE set to `1'. See Figure 16.1 for the memory map under different COBANK and SFLE set-
tings.

16.1.2. Erasing FLASH Pages From Software

When erasing FLASH memory, an entire page is erased (all bytes in the page are set to 0xFF). The 128k byte
FLASH memory is organized in 1024-byte pages. The 256 bytes of Scratchpad area (addresses 0x20000 to 0x200FF)
consists of two 128 byte pages. To erase any FLASH page, the FLWE, PSWE, and PSEE bits must be set to `1', and
a byte must be written using a MOVX instruction to any address within that page. The following is the recommended
procedure for erasing a FLASH page from software:

Step 1. Disable interrupts.
Step 2. If erasing a page in Bank 1, Bank 2, or Bank 3, set the COBANK bits (PSBANK.5-4) for the

appropriate bank.

Step 3. If erasing a page in the Scratchpad area, set the SFLE bit (PSCTL.2).
Step 4. Set FLWE (FLSCL.0) to enable FLASH writes/erases via user software.
Step 5. Set PSEE (PSCTL.1) to enable FLASH erases.
Step 6. Set PSWE (PSCTL.0) to redirect MOVX commands to write to FLASH.
Step 7. Use the MOVX instruction to write a data byte to any location within the page to be erased.
Step 8. Clear PSEE to disable FLASH erases.
Step 9. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 10. Clear the FLWE bit, to disable FLASH writes/erases.
Step 11. If erasing a page in the Scratchpad area, clear the SFLE bit.
Step 12. Re-enable interrupts.

Bank 0

Bank 1

Bank 2

Bank 3

Bank 0

COBANK = 0 COBANK = 1 COBANK = 2 COBANK = 3

SFLE = 0

SFLE = 1

Internal

Address

0x0000

0x7FFF

0x8000

0xFFFF

Undefined

Scratchpad

Areas (2)

0x00FF

Figure 16.1. FLASH Memory Map for MOVC Read and MOVX Write Operations

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16.1.3. Writing FLASH Memory From Software

Bytes in FLASH memory can be written one byte at a time, or in small blocks. The CHBLKW bit in register
CCH0CN (Figure 17.4) controls whether a single byte or a block of bytes is written to FLASH during a write opera-
tion. When CHBLKW is cleared to `0', the FLASH will be written one byte at a time. When CHBLKW is set to `1',
the FLASH will be written in blocks of four bytes for addresses in code space, or blocks of two bytes for addresses in
the Scratchpad area. Block writes are performed in the same amount of time as single byte writes, which can save
time when storing large amounts of data to FLASH memory.

For single-byte writes to FLASH, bytes are written individually, and the FLASH write is performed after each
MOVX write instruction. The recommended procedure for writing FLASH in single bytes is:

Step 1. Disable interrupts.
Step 2. Clear CHBLKW (CCH0CN.0) to select single-byte write mode.
Step 3. If writing to bytes in Bank 1, Bank 2, or Bank 3, set the COBANK bits (PSBANK.5-4) for the

appropriate bank.

Step 4. If writing to bytes in the Scratchpad area, set the SFLE bit (PSCTL.2).
Step 5. Set FLWE (FLSCL.0) to enable FLASH writes/erases via user software.
Step 6. Set PSWE (PSCTL.0) to redirect MOVX commands to write to FLASH.
Step 7. Use the MOVX instruction to write a data byte to the desired location (repeat as necessary).
Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 9. Clear the FLWE bit, to disable FLASH writes/erases.
Step 10. If writing to bytes in the Scratchpad area, clear the SFLE bit.
Step 11. Re-enable interrupts.

For block FLASH writes, the FLASH write procedure is only performed after the last byte of each block is written
with the MOVX write instruction. When writing to addresses located in any of the four code banks, a FLASH write
block is four bytes long, from addresses ending in 00b to addresses ending in 11b. Writes must be performed sequen-
tially (i.e. addresses ending in 00b, 01b, 10b, and 11b must be written in order). The FLASH write will be performed
following the MOVX write that targets the address ending in 11b. When writing to addresses located in the FLASH
Scratchpad area, a FLASH block is two bytes long, from addresses ending in 0b to addresses ending in 1b. The
FLASH write will be performed following the MOVX write that targets the address ending in 1b. If any bytes in the
block do not need to be updated in FLASH, they should be written to 0xFF. The recommended procedure for writing
FLASH in blocks is:

Step 1. Disable interrupts.
Step 2. Set CHBLKW (CCH0CN.0) to select block write mode.
Step 3. If writing to bytes in Bank 1, Bank 2, or Bank 3, set the COBANK bits (PSBANK.5-4) for the

appropriate bank.

sequentially, and the last byte written must be the high byte of the block (see text for details, repeat as
necessary).

Step 8. Clear the PSWE bit to redirect MOVX commands to the XRAM data space.
Step 9. Clear the FLWE bit, to disable FLASH writes/erases.
Step 10. If writing to bytes in the Scratchpad area, clear the SFLE bit.
Step 11. Re-enable interrupts.

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Write/Erase timing is automatically controlled by hardware. Note that 1024 bytes beginning at location 0x1FC00 are
reserved. FLASH writes and erases targeting the reserved area should be avoided.

16.2.

Security Options

The CIP-51 provides security options to protect the FLASH memory from inadvertent modification by software as
well as prevent the viewing of proprietary program code and constants. The Program Store Write Enable (PSCTL.0),
Program Store Erase Enable (PSCTL.1), and Flash Write/Erase Enable (FLACL.0) bits protect the FLASH memory
from accidental modification by software. These bits must be explicitly set to logic 1 before software can write or
erase the FLASH memory. Additional security features prevent proprietary program code and data constants from
being read or altered across the JTAG interface or by software running on the system controller.

A set of security lock bytes stored at 0x1FBFF and 0x1FBFE protect the FLASH program memory from being read
or altered across the JTAG interface. Each bit in a security lock-byte protects one 16k-byte block of memory. Access
to the scratchpad area can only be locked by locking all other FLASH blocks. Clearing a bit to logic 0 in a Read Lock
Byte prevents the corresponding block of FLASH memory from being read across the JTAG interface. Clearing a bit
in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes. The Read Lock Byte is at location
0x1FBFF. The Write/Erase Lock Byte is located at 0x1FBFE. Figure 16.2 shows the location and bit definitions of
the security bytes. The 1024-byte sector containing the lock bytes can be written to, but not erased by software. An
attempted read of a read-locked byte returns undefined data. Debugging code in a read-locked sector is not possible
through the JTAG interface. To ensure protection from external access, the block containing the lock bytes
(1C000-1BFFF) must be write/erase locked by clearing the MSB of byte 0x1FBFE.

Table 16.1. FLASH Electrical Characteristics

VDD = 2.7 to 3.6 V; -40°C to +85°C

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Endurance

20k

100k

Erase/Write

Erase Cycle Time

Write Cycle Time

µs

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The lock bits can always be read and cleared to logic 0 regardless of the security setting applied to the block contain-
ing the security bytes. This allows additional blocks to be protected after the block containing the security bytes has
been locked. Important Note: The only means of removing a lock once the MSB of the write/erase lock security
byte is set is to erase the entire program memory space by performing a JTAG erase operation (i.e. cannot be
done in user firmware). Addressing either security byte while performing a JTAG erase operation will auto-
matically initiate erasure of the entire program memory space (except for the reserved area). This erasure can
only be performed via JTAG. If a non-security byte in the 0x1F800-0x1FBFF page is addressed during the
JTAG erasure, only that page (including the security bytes) will be erased.

0x1FC00

0x1FBFE

Program/Data

Memory Space

0x00000

0x1FBFF

Read Lock Byte

Write/Erase Lock Byte

Software Read Limit

Reserved

0x1FFFF

0x1FBFD

SFLE = 0

Bit

Memory Block

7
6
5
4

0x18000 - 0x1BFFF

0x1C000 - 0x1FBFD

0x14000 - 0x17FFF
0x10000 - 0x13FFF

3
2
1
0

0x08000 - 0x0BFFF

0x0C000 - 0x0FFFF

0x04000 - 0x07FFF
0x00000 - 0x03FFF

Read and Write/Erase Security Bits.
(Bit7 is MSB.)

0x00FF

0x0000

Scratchpad Memory

(Data only)

SFLE = 1

Figure 16.2. FLASH Program Memory Map and Security Bytes

FLASH Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit7 is MSB).

0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.

FLASH Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.

0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
NOTE: When the highest block is locked, the security bytes may be written but not erased.

FLASH access Limit Register (FLACL)

The content of this register is used as the 8 MSBs of the 17-bit software read limit address. Software
running at or above this address is prohibited from using the MOVX and MOVC instructions to read,
write, or erase FLASH locations below this address. Any attempts to read locations below this limit
will return indeterminate data.

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The FLASH Access Limit security feature (see Figure 16.2) protects proprietary program code and data from being
read by software running on the C8051F120/1/2/3/4/5/6/7. This feature provides support for OEMs that wish to pro-
gram the MCU with proprietary value-added firmware before distribution. The value-added firmware can be pro-
tected while allowing additional code to be programmed in remaining program memory space later.

The Software Read Limit (SRL) is a 17-bit address that establishes two logical partitions in the program memory
space. The first is an upper partition consisting of all the program memory locations at or above the SRL address, and
the second is a lower partition consisting of all the program memory locations starting at 0x00000 up to (but exclud-
ing) the SRL address. Software in the upper partition can execute code in the lower partition, but is prohibited from
reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the upper
partition with a source address in the lower partition will return indeterminate data.) Software running in the lower
partition can access locations in both the upper and lower partition without restriction.

The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added
firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a predeter-
mined location in the upper partition. If entry points are published, software running in the upper partition may exe-
cute program code in the lower partition, but it cannot read or change the contents of the lower partition. Parameters
may be passed to the program code running in the lower partition either through the typical method of placing them
on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.

The SRL address is specified using the contents of the FLASH Access Register. The 8 MSBs of the 17-bit SRL
address are determined by the setting of the FLACL register. Thus, the SRL can be located on 512-byte boundaries
anywhere in program memory space. However, the 1024-byte erase sector size essentially requires that a 1024
boundary be used. The contents of a non-initialized FLACL security byte are 0x00, thereby setting the SRL address
to 0x00000 and allowing read access to all locations in program memory space by default.

Bits 7-0:

FLACL: FLASH Access Limit.
This register holds the most significant 8 bits of the 17-bit program memory read/write/erase limit
address. The lower 9 bits of the read/write/erase limit are always set to 0. A write to this register sets
the FLASH Access Limit. This register can only be written once after any reset. Any subsequent
writes are ignored until the next reset. To fully protect all addresses below this limit, bit 0 of FLACL
should be set to `0'.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xB7
F

Figure 16.3. FLACL: FLASH Access Limit

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Figure 16.5. PSCTL: Program Store Read/Write Control

Bits 7-3:

UNUSED. Read = 00000b, Write = don't care.

Bit 2:

SFLE: Scratchpad FLASH Memory Access Enable
When this bit is set, FLASH MOVC reads and writes from user software are directed to the two 128-
byte Scratchpad FLASH sectors. When SFLE is set to logic 1, FLASH accesses out of the address
range 0x00-0xFF should not be attempted (with the exception of address 0x400, which can be used to
simultaneously erase both Scratchpad areas). Reads/Writes out of this range will yield undefined
results.
0: FLASH access from user software directed to the 128k byte Program/Data FLASH sector.
1: FLASH access from user software directed to the two 128 byte Scratchpad sectors.

Bit 1:

PSEE: Program Store Erase Enable.
Setting this bit allows an entire page of the FLASH program memory to be erased provided the
PSWE bit is also set. After setting this bit, a write to FLASH memory using the MOVX instruction
will erase the entire page that contains the location addressed by the MOVX instruction. The value of
the data byte written does not matter. Note: The FLASH page containing the Read Lock Byte and
Write/Erase Lock Byte cannot be erased by software.
0: FLASH program memory erasure disabled.
1: FLASH program memory erasure enabled.

Bit 0:

PSWE: Program Store Write Enable.
Setting this bit allows writing a byte of data to the FLASH program memory using the MOVX write
instruction. The location must be erased prior to writing data.
0: Write to FLASH program memory disabled. MOVX write operations target External RAM.
1: Write to FLASH program memory enabled. MOVX write operations target FLASH memory.

R/W

Reset Value

SFLE

PSEE

PSWE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8F
0

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17.

BRANCH TARGET CACHE

The C8051F12x family of devices incorporate a 63x4 byte branch target cache with a 4-byte prefetch engine.
Because the access time of the FLASH memory is 40ns, and the minimum instruction time is 10ns (C8051F120/1/2/
3) or 20ns (C8051F124/5/6/7), the branch target cache and prefetch engine are necessary for full-speed code execu-
tion. Instructions are read from FLASH memory four bytes at a time by the prefetch engine, and given to the CIP-51
processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine alone
allows instructions to be executed at full speed. When a code branch occurs, a search is performed for the branch tar-
get (destination address) in the cache. If the branch target information is found in the cache (called a "cache hit"), the
instruction data is read from the cache and immediately returned to the CIP-51 with no delay in code execution. If the
branch target is not found in the cache (called a "cache miss"), the processor may be stalled for up to four clock
cycles while the next set of four instructions is retrieved from FLASH memory. Each time a cache miss occurs, the
requested instruction data is written to the cache if allowed by the current cache settings. A data flow diagram of the
interaction between the CIP-51 and the Branch Target Cache and Prefetch Engine is shown in Figure 17.1.

17.1.

Cache and Prefetch Operation

The branch target cache maintains two sets of memory locations: "slots" and "tags". A slot is where the cached
instruction data from FLASH is stored. Each slot holds four consecutive code bytes. A tag contains the 15 most sig-
nificant bits of the corresponding FLASH address for each four-byte slot. Thus, instruction data is always cached
along four-byte boundaries in code space. A tag also contains a "valid bit", which indicates whether a cache location
contains valid instruction data. A special cache location (called the linear tag and slot), is reserved for use by the
prefetch engine. The cache organization is shown in Figure 17.2. Each time a FLASH read is requested, the address is
compared with all valid cache tag locations (including the linear tag). If any of the tag locations match the requested
address, the data from that slot is immediately provided to the CIP-51. If the requested address matches a location
that is currently being read by the prefetch engine, the CIP-51 will be stalled until the read is complete. If a match is
not found, the current prefetch operation is abandoned, and a new prefetch operation is initiated for the requested
instruction data. When the prefetch operation is finished, the CIP-51 begins executing the instructions that were
retrieved, and the prefetch engine begins reading the next four-byte word from FLASH memory. If the newly-fetched
data also meets the criteria necessary to be cached, it will be written to the cache in the slot indicated by the current
replacement algorithm.

The replacement algorithm is selected with the Cache Algorithm bit, CHALGM (CCH0TN.3). When CHALGM is
cleared to `0', the cache will use the rebound algorithm to replace cache locations. The rebound algorithm replaces
locations in order from the beginning of cache memory to the end, and then from the end of cache memory to the

FLASH

Memory

Branch Target

Cache

Prefetch

Engine

Instruction

Data

CIP-51

Instruction Address

Figure 17.1. Branch Target Cache Data Flow

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beginning. When CHALGM is set to `1', the cache will use the pseudo-random algorithm to replace cache locations.
The pseudo-random algorithm uses a pseudo-random number to determine which cache location to replace. The
cache can be manually emptied by writing a `1' to the CHFLUSH bit (CCH0CN.4).

17.2.

Cache and Prefetch Optimization

By default, the branch target cache is configured to provide code speed improvements for a broad range of circum-
stances. In most applications, the cache control registers should be left in their reset states. Sometimes it is
desirable to optimize the execution time of a specific routine or critical timing loop. The branch target cache includes
options to exclude caching of certain types of data, as well as the ability to pre-load and lock time-critical branch
locations to optimize execution speed.

The most basic level of cache control is implemented with the Cache Miss Penalty Threshold bits, CHMSTH
(CCH0TN.1-0). If the processor is stalled during a prefetch operation for more clock cycles than the number stored
in CHMSTH, the requested data will be cached when it becomes available. The CHMSTH bits are set to zero by
default, meaning that any time the processor is stalled, the new data will be cached. If, for example, CHMSTH is
equal to 2, any cache miss causing a delay of 3 or 4 clock cycles will be cached, while a cache miss causing a delay of
1-2 clock cycles will not be cached.

Certain types of instruction data or certain blocks of code can also be excluded from caching. The destinations of
RETIinstructions are, by default, excluded from caching. To enable caching of RETIdestinations, the CHRETIbit
(CCH0CN.3) can be set to `1'. It is generally not beneficial to cache RETI destinations unless the same instruction is

SLOT = 4 Instruction

Data Bytes

TAG 58

SLOT 58

V58

TAG 62

SLOT 62

V62

TAG 61

SLOT 61

V61

TAG 2

SLOT 2

TAG 1

SLOT 1

TAG 0

SLOT 0

TAG 60

SLOT 60

V60

TAG 59

SLOT 59

V59

LINEAR TAG

LINEAR SLOT

Prefetch Data

Valid

Bit

Address

Data

Cache Data

TAG = 15 MSBs of Absolute FLASH Address

A16

A1 A0

Byte 0

Byte 1

Byte 2

Byte 3

Figure 17.2. Branch Target Cache Organiztion

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likely to be interrupted repeatedly (such as a code loop that is waiting for an interrupt to happen). Instructions that are
part of an interrupt service routine (ISR) can also be excluded from caching. By default, ISR instructions are cached,
but this can be disabled by clearing the CHISR bit (CCH0CN.2) to `0'. The other information that can be explicitly
excluded from caching are the data returned by MOVC instructions. Clearing the CHMOV bit (CCH0CN.1) to `0'
will disable caching of MOVC data. If MOVC caching is allowed, it can be restricted to only use slot 0 for the
MOVC information (excluding cache push operations). The CHFIXM bit (CCH0TN.2) controls this behavior.

Further cache control can be implemented by disabling all cache writes. Cache writes can be disabled by clearing the
CHWREN bit (CCH0CN.7) to `0'. Although normal cache writes (such as those after a cache miss) are disabled, data
can still be written to the cache with a cache push operation. Disabling cache writes can be used to prevent a non-crit-
ical section of code from changing the cache contents. Note that regardless of the value of CHWREN, a FLASH
write or erase operation automatically removes the affected bytes from the cache. Cache reads and the prefetch engine
can also be individually disabled. Disabling cache reads forces all instructions data to execute from FLASH memory
or from the prefetch engine. To disable cache reads, the CHRDEN bit (CCH0CN.6) can be cleared to `0'. Note that
when cache reads are disabled, cache writes will still occur (if CHWREN is set to `1'). Disabling the prefetch engine
is accomplished using the CHPFEN bit (CCH0CN.5). When this bit is cleared to `0', the prefetch engine will be dis-
abled. If both CHPFEN and CHRDEN are `0', code will execute at a fixed rate, as instructions become available
from the FLASH memory.

Cache locations can also be pre-loaded and locked with time-critical branch destinations. For example, in a system
with an ISR that must respond as fast as possible, the entry point for the ISR can be locked into a cache location to
minimize the response latency of the ISR. Up to 61 locations can be locked into the cache at one time. Instructions
are locked into cache by enabling cache push operations with the CHPUSH bit (CCH0LC.7). When CHPUSH is set
to `1', a MOVC instruction will cause the four-byte segment containing the data byte to be written to the cache slot
location indicated by CHSLOT (CCH0LC.5-0). CHSLOT is them decremented to point to the next lockable cache
location. This process is called a cache push operation. Cache locations that are above CHSLOT are "locked", and
cannot be changed by the processor core, as shown in Figure 17.3. Cache locations can be unlocked by using a cache
pop operation. A cache pop is performed by writing a `1' to the CHPOP bit (CCH0LC.6). When a cache pop is ini-
tiated, the value of CHSLOT is incremented. This unlocks the most recently locked cache location, but does not
remove the information from the cache. Note that a cache pop should not be initiated if CHSLOT is equal to 111110b.
Doing so may have an adverse effect on cache performance. Important: Although locking cache location 1 is not
explicitly disabled by hardware, the entire cache will be unlocked when CHSLOT is equal to 000000b. There-
fore, cache locations 1 and 0 must remain unlocked at all times.

TAG 62

SLOT 62

TAG 61

SLOT 61

TAG 2

SLOT 2

TAG 1

SLOT 1

TAG 0

SLOT 0

TAG 60

SLOT 60

TAG 59

SLOT 59

CHSLOT = 58

LOCKED

UNLOCKED

Lock Status

Cache Push

Operations
Decrement

CHSLOT

Cache Pop
Operations

Increment

CHSLOT

LOCKED

TAG 58

SLOT 58

UNLOCKED

TAG 57

SLOT 57

UNLOCKED

Figure 17.3. Cache Lock Operation

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Figure 17.4. CCH0CN: Cache Control Register

Bit 7:

CHWREN: Cache Write Enable.
This bit enables the processor to write to the cache memory.
0: Cache contents are not allowed to change, except during FLASH writes/erasures or cache locks.
1: Writes to cache memory are allowed.

Bit 6:

CHRDEN: Cache Read Enable.
This bit enables the processor to read instructions from the cache memory.
0: All instruction data comes from FLASH memory or the prefetch engine.
1: Instruction data is obtained from cache (when available).

Bit 5:

CHPFEN: Cache Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.

Bit 4:

CHFLSH: Cache Flush.
When written to a `1', this bit clears the cache contents. This bit always reads `0'.

Bit 3:

CHRETI: Cache RETI Destination Enable.
This bit enables the destination of a RETIaddress to be cached.
0: Destinations of RETIinstructions will not be cached.
1: RETIdestinations will be cached.

Bit 2:

CHISR: Cache ISR Enable.
This bit allows instructions which are part of an Interrupt Service Rountine (ISR) to be cached.
0: Instructions in ISRs will not be loaded into cache memory.
1: Instructions in ISRs can be cached.

Bit 1:

CHMOVC: Cache MOVC Enable.
This bit allows data requested by a MOVC instruction to be loaded into the cache memory.
0: Data requested by MOVC instructions will not be cached.
1: Data requested by MOVC instructions will be loaded into cache memory.

Bit 0:

CHBLKW: Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of four (for code space writes) or two (for scratchpad writes).

R/W

Reset Value

CHWREN CHRDEN

CHPFEN

CHFLSH

CHRETICHI

CHMOVC CHBLKW 11100110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA1
F

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Figure 17.5. CCH0TN: Cache Tuning Register

Bits 7-4:

CHMSCTL: Cache Miss Penalty Accumulator (Bits 4-1).
These are bits 4-1 of the Cache Miss Penalty Accumulator. To read these bits, they must first be
latched by reading the CHMSCTH bits in the CCH0MA Register (See Figure 17.7).

Bit 3:

CHALGM: Cache Algorithm Select.
This bit selects the cache replacement algorithm.
0: Cache uses Rebound algorithm.
1: Cache uses Pseudo-random algorithm.

Bit 2:

CHFIXM: Cache Fix MOVC Enable.
This bit forces MOVC writes to the cache memory to use slot 0.
0: MOVC data is written according to the current algorithm selected by the CHALGM bit.
1: MOVC data is always written to cache slot 0.

Bits 1-0:

CHMSTH: Cache Miss Penalty Threshold.
These bits determine when missed instruction data will be cached.
If data takes longer than CHMSTH clocks to obtain, it will be cached.

R/W

Reset Value

CHMSCTL

CHALGM CHFIXM

CHMSTH

00000100

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA2
F

Figure 17.6. CCH0LC: Cache Lock Control Register

Bit 7:

CHPUSH: Cache Push Enable.
This bit enables cache push operations, which will lock information in cache slots using MOVC
instructions.
0: Cache push operations are disabled.
1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-byte segment
containing the data is locked into the cache at the location indicated by CHSLOT, and CHSLOT is
decremented.
Note that no more than 61 cache slots should be locked at one time, since the entire cache will be
unlocked when CHSLOT is equal to 0.

Bit 6:

CHPOP: Cache Pop.
Writing a `1' to this bit will increment CHSLOT and then unlock that location. This bit always reads
`0'. Note that Cache Pop operations should not be performed while CHSLOT = 111110b. "Pop"ing
more Cache slots than have been "Push"ed will have indeterminate results on the Cache performance.

Bits 5-0:

CHSLOT: Cache Slot Pointer.
These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are locked,
and will not be changed by the processor, except when CHSLOT equals 0.

R/W

Reset Value

CHPUSH

CHPOP

CHSLOT

00111110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA3
F

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Figure 17.7. CCH0MA: Cache Miss Accumulator

Bit 7:

CHMSOV: Cache Miss Penalty Overflow.
This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was last written.
0: The Cache Miss Penalty Accumulator has not overflowed since it was last written.
1: An overflow of the Cache Miss Penalty Accumulator has occurred since it was last written.

Bits 6-0:

CHMSCTH: Cache Miss Penalty Accumulator (bits 11-5)
These are bits 11-5 of the Cache Miss Penalty Accumulator. The next four bits (bits 4-1) are stored in
CHMSCTL in the CCH0TN register.
The Cache Miss Penalty Accumulator is incremented every clock cycle that the processor is delayed
due to a cache miss. This is primarily used as a diagnostic feature, when optimizing code for execu-
tion speed.
Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator.
Reading from CHMSCTH returns the current value of CHMSTCH, and latches bits 4-1 into CHM-
STCL so that they can be read. Because bit 0 of the Cache Miss Penalty Accumulator is not avail-
able, the Cumulative Miss Penalty is equal to 2 * (CCHMSTCH:CCHMSTCL).

R/W

Reset Value

CHMSOV

CHMSCTH

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9A
F

Figure 17.8. FLSTAT: FLASH Status

Bit 7-1:

Reserved.

Bit 0:

FLBUSY: FLASH Busy
This bit indicates when a FLASH write or erase operation is in progress.
0: FLASH is idle or reading.
1: FLASH write/erase operation is currently in progress.

R/W

Reset Value

FLBUSY

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x88
F

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18.

EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM

The C8051F12x MCUs include 8k bytes of on-chip RAM mapped into the external data memory space (XRAM), as
well as an External Data Memory Interface which can be used to access off-chip memories and memory-mapped
devices connected to the GPIO ports. The external memory space may be accessed using the external move instruc-
tion (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If the
MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is
provided by the External Memory Interface Control Register (EMI0CN, shown in Figure 18.1). Note: the MOVX
instruction can also be used for writing to the FLASH memory. See

Section "16. FLASH MEMORY" on page 185

for details. The MOVX instruction accesses XRAM by default. The EMIF can be configured to appear on the lower
GPIO Ports (P0-P3) or the upper GPIO Ports (P4-P7).

18.1.

Accessing XRAM

The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of
which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which con-
tains the effective address of the XRAM location to be read from or written to. The second method uses R0 or R1 in
combination with the EMI0CN register to generate the effective XRAM address. Examples of both of these methods
are given below.

18.1.1. 16-Bit MOVX Example

The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR reg-
ister. The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A:

MOV

DPTR, #1234h

; load DPTR with 16-bit address to read (0x1234)

MOVX

A, @DPTR

; load contents of 0x1234 into accumulator A

The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately, the DPTR
can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains
the lower 8-bits of DPTR.

18.1.2. 8-Bit MOVX Example

The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the
effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to
be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator
A.

MOV

EMI0CN, #12h

; load high byte of address into EMI0CN

MOV

R0, #34h

; load low byte of address into R0 (or R1)

MOVX

a, @R0

; load contents of 0x1234 into accumulator A

18.2.

Configuring the External Memory Interface

Configuring the External Memory Interface consists of five steps:

Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4).

Configure the Output Modes of the port pins as either push-pull or open-drain (push-pull is most com-

mon).
3.

Configure Port latches to "park" the EMIF pins in a dormant state (usually by setting them to logic `1').

Select Multiplexed mode or Non-multiplexed mode.

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Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or

off-chip only).
6.

Set up timing to interface with off-chip memory or peripherals.

Each of these five steps is explained in detail in the following sections. The Port selection, Multiplexed mode selec-
tion, and Mode bits are located in the EMI0CF register shown in Figure 18.2.

18.3.

Port Selection and Configuration

The External Memory Interface can appear on Ports 3, 2, 1, and 0 (C8051F120/1/2/3/4/5/6/7 devices) or on Ports 7, 6,
5, and 4 (C8051F120/2/4/6 devices only), depending on the state of the PRTSEL bit (EMI0CF.5). If the lower Ports
are selected, the EMIFLE bit (XBR2.1) must be set to a `1' so that the Crossbar will skip over P0.7 (/WR), P0.6 (/
RD), and if multiplexed mode is selected P0.5 (ALE). For more information about the configuring the Crossbar, see

Section "19.1. Ports 0 through 3 and the Priority Crossbar Decoder" on page 217

The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of
an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port pins reverts to the Port
latches or to the Crossbar (on Ports 3, 2, 1, and 0). See

Section "19. PORT INPUT/OUTPUT" on page 215

for

more information about the Crossbar and Port operation and configuration. The Port latches should be explicitly
configured to `park' the External Memory Interface pins in a dormant state, most commonly by setting them
to a logic 1.

During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the drivers on
all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output mode of the Port
pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface oper-
ation, and remains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be
configured for push-pull mode. See"Configuring the Output Modes of the Port Pins" on page 218.

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Figure 18.1. EMI0CN: External Memory Interface Control

Bits7-0:

PGSEL[7:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when
using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF

R/W

Reset Value

PGSEL7

PGSEL6

PGSEL5

PGSEL4

PGSEL3

PGSEL2

PGSEL1

PGSEL0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA2
0

Figure 18.2. EMI0CF: External Memory Configuration

Bits7-6:

Unused. Read = 00b. Write = don't care.

Bit5:

PRTSEL: EMIF Port Select.
0: EMIF active on P0-P3.
1: EMIF active on P4-P7.

Bit4:

EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).

Bits3-2:

EMD1-0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip
memory space.
01: Split Mode without Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses
above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the current contents
of the Address High port latches to resolve upper address byte. Note that in order to access off-chip
space, EMI0CN must be set to a page that is not contained in the on-chip address space.
10: Split Mode with Bank Select: Accesses below the 8k boundary are directed on-chip. Accesses
above the 8k boundary are directed off-chip. 8-bit off-chip MOVX operations use the contents of
EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.

Bits1-0:

EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.

R/W

Reset Value

PRTSEL

EMD2

EMD1

EMD0

EALE1

EALE0

00000011

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA3
0

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18.4.

Multiplexed and Non-multiplexed Selection

The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending
on the state of the EMD2 (EMI0CF.4) bit.

18.4.1. Multiplexed Configuration

In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0]. In this
mode, an external latch (74HC373 or equivalent logic gate) is used to hold the lower 8-bits of the RAM address. The
external latch is controlled by the ALE (Address Latch Enable) signal, which is driven by the External Memory Inter-
face logic. An example of a Multiplexed Configuration is shown in Figure 18.3.

In Multiplexed mode, the external MOVX operation can be broken into two phases delineated by the state of the ALE
signal. During the first phase, ALE is high and the lower 8-bits of the Address Bus are presented to AD[7:0]. During
this phase, the address latch is configured such that the `Q' outputs reflect the states of the `D' inputs. When ALE
falls, signaling the beginning of the second phase, the address latch outputs remain fixed and are no longer dependent
on the latch inputs. Later in the second phase, the Data Bus controls the state of the AD[7:0] port at the time /RD or /
WR is asserted.

See

Section "18.6.2. Multiplexed Mode" on page 210

for more information.

ADDRESS/DATA BUS

ADDRESS BUS

E
M
I
F

A[15:8]

AD[7:0]

/WR

/RD

ALE

64K X 8

SRAM

I/O[7:0]

74HC373

A[15:8]

A[7:0]

(Optional)

Figure 18.3. Multiplexed Configuration Example

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18.5.

Memory Mode Selection

The external data memory space can be configured in one of four modes, shown in Figure 18.5, based on the EMIF
Mode bits in the EMI0CF register (Figure 18.2). These modes are summarized below. More information about the
different modes can be found in

Section "18.6. Timing" on page 206

18.5.1. Internal XRAM Only

When EMI0CF.[3:2] are set to `00', all MOVX instructions will target the internal XRAM space on the device. Mem-
ory accesses to addresses beyond the populated space will wrap on 8k boundaries. As an example, the addresses
0x2000 and 0x4000 both evaluate to address 0x0000 in on-chip XRAM space.

8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0
or R1 to determine the low-byte of the effective address.

16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.

18.5.2. Split Mode without Bank Select

When EMI0CF.[3:2] are set to `01', the XRAM memory map is split into two areas, on-chip space and off-chip space.

Effective addresses below the 8k boundary will access on-chip XRAM space.

Effective addresses above the 8k boundary will access off-chip space.

8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. However, in the "No Bank Select" mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8]
of the Address Bus during an off-chip access. This allows the user to manipulate the upper address bits at will by
setting the Port state directly via the port latches. This behavior is in contrast with "Split Mode with Bank Select"
described below. The lower 8-bits of the Address Bus A[7:0] are driven, determined by R0 or R1.

16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-
chip transaction.

EMI0CF[3:2] = 00

0xFFFF

0x0000

EMI0CF[3:2] = 11

0xFFFF

0x0000

EMI0CF[3:2] = 01

0xFFFF

0x0000

EMI0CF[3:2] = 10

On-Chip XRAM

Off-Chip

Memory

(No Bank Select)

On-Chip XRAM

0xFFFF

0x0000

Off-Chip

Memory

(Bank Select)

On-Chip XRAM

Off-Chip

Memory

Figure 18.5. EMIF Operating Modes

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18.5.3. Split Mode with Bank Select

When EMI0CF.[3:2] are set to `10', the XRAM memory map is split into two areas, on-chip space and off-chip space.

Effective addresses below the 8k boundary will access on-chip XRAM space.

Effective addresses above the 8k boundary will access off-chip space.

8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the
Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in "Bank
Select" mode.

16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.

18.5.4. External Only

When EMI0CF[3:2] are set to `11', all MOVX operations are directed to off-chip space. On-chip XRAM is not visi-
ble to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 8k boundary.

8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identi-
cal behavior to an off-chip access in "Split Mode without Bank Select" described above). This allows the user to
manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective
address A[7:0] are determined by the contents of R0 or R1.

16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits
of the Address Bus A[15:0] are driven during the off-chip transaction.

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18.6.

Timing

The timing parameters of the External Memory Interface can be configured to enable connection to devices having
different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths,
and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through
EMI0TC, shown in Figure 18.6, and EMI0CF[1:0].

The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters
defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip
XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed opera-
tions, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the mini-
mum execution time for an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 for /ALE + 1 for
/RD or /WR + 4). The programmable setup and hold times default to the maximum delay settings after a reset.

Table 18.1 lists the AC parameters for the External Memory Interface, and Figure 18.7 through Figure 18.12 show the
timing diagrams for the different External Memory Interface modes and MOVX operations.

Figure 18.6. EMI0TC: External Memory Timing Control

Bits7-6:

EAS1-0: EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.

Bits5-2:

EWR3-0: EMIF /WR and /RD Pulse-Width Control Bits.
0000: /WR and /RD pulse width = 1 SYSCLK cycle.
0001: /WR and /RD pulse width = 2 SYSCLK cycles.
0010: /WR and /RD pulse width = 3 SYSCLK cycles.
0011: /WR and /RD pulse width = 4 SYSCLK cycles.
0100: /WR and /RD pulse width = 5 SYSCLK cycles.
0101: /WR and /RD pulse width = 6 SYSCLK cycles.
0110: /WR and /RD pulse width = 7 SYSCLK cycles.
0111: /WR and /RD pulse width = 8 SYSCLK cycles.
1000: /WR and /RD pulse width = 9 SYSCLK cycles.
1001: /WR and /RD pulse width = 10 SYSCLK cycles.
1010: /WR and /RD pulse width = 11 SYSCLK cycles.
1011: /WR and /RD pulse width = 12 SYSCLK cycles.
1100: /WR and /RD pulse width = 13 SYSCLK cycles.
1101: /WR and /RD pulse width = 14 SYSCLK cycles.
1110: /WR and /RD pulse width = 15 SYSCLK cycles.
1111: /WR and /RD pulse width = 16 SYSCLK cycles.

Bits1-0:

EAH1-0: EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.

R/W

Reset Value

EAS1

EAS0

ERW3

EWR2

EWR1

EWR0

EAH1

EAH0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA1
0

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19.

PORT INPUT/OUTPUT

The C8051F12x family of devices are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins
(C8051F120/2/4/6) or 32 digital I/O pins (C8051F121/3/5/7), organized as 8-bit Ports. All ports are both bit- and
byte-addressable through their corresponding Port Data registers. All Port pins are 5 V-tolerant, and all support con-
figurable Open-Drain or Push-Pull output modes and weak pull-ups. A block diagram of the Port I/O cell is shown in
Figure 19.1. Complete Electrical Specifications for the Port I/O pins are given in Table 19.1.

DGND

/PORT-OUTENABLE

PORT-OUTPUT

PUSH-PULL

VDD

/WEAK-PULLUP

(WEAK)

PORT
PAD

ANALOG INPUT

Analog Select
(Ports 1, 2, and 3)

PORT-INPUT

Figure 19.1. Port I/O Cell Block Diagram

Table 19.1. Port I/O DC Electrical Characteristics

VDD = 2.7 V to 3.6 V, -40°C to +85°C unless otherwise specified.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output High Voltage (V

) I

= -3 mA, Port I/O Push-Pull

= -10 µA, Port I/O Push-Pull

= -10 mA, Port I/O Push-Pull

VDD - 0.7
VDD - 0.1

VDD-0.8

Output Low Voltage (V

) I

= 8.5 mA

= 10 µA

= 25 mA

1.0

0.6
0.1

Input High Voltage (VIH)

0.7 x VDD

Input Low Voltage (VIL)

0.3 x

VDD

Input Leakage Current

DGND < Port Pin < VDD, Pin Tri-state
Weak Pull-up Off
Weak Pull-up On

± 1

µA

Input Capacitance

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The C8051F12x family of devices have a wide array of digital resources which are available through the four lower I/
O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO)
pin or can be controlled by a digital peripheral or function (like UART0 or /INT1 for example), as shown in
Figure 19.2. The system designer controls which digital functions are assigned pins, limited only by the number of
pins available. This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note
that the state of a Port I/O pin can always be read from its associated Data register regardless of whether that pin has
been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as Analog Inputs to
ADC2.

An External Memory Interface which is active during the execution of an off-chip MOVX instruction can be active
on either the lower Ports or the upper Ports. See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND

ON-CHIP XRAM" on page 199

for more information about the External Memory Interface.

External

Pins

Digital

Crossbar

Priority

Decoder

SMBus

SPI

UART0

PCA

T0, T1,

T2, T2EX,

T4,T4EX

/INT0,

/INT1

P1.0

P1.7

P2.0

P2.7

P0.0

P0.7

Highest

Priority

Lowest
Priority

Comptr.
Outputs

(
I
ntern

igital

i
g

nals)

Highest

Priority

Lowest

Priority

UART1

/SYSCLK divided by 1,2,4, or 8

CNVSTR0/2

P3.0

P3.7

P0MDOUT, P1MDOUT,

P2MDOUT, P3MDOUT

Registers

XBR0, XBR1,

XBR2, P1MDIN

Registers

I/O

Cells

I/O

Cells

I/O

Cells

I/O

Cells

Port

Latches

(P2.0-P2.7)

(P1.0-P1.7)

(P0.0-P0.7)

(P3.0-P3.7)

ADC2

Input

To External

Memory

Interface

(EMIF)

Figure 19.2. Port I/O Functional Block Diagram

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19.1.

Ports 0 through 3 and the Priority Crossbar Decoder

The Priority Crossbar Decoder, or "Crossbar", allocates and assigns Port pins on Port 0 through Port 3 to the digital
peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in
order starting with P0.0 and continue through P3.7 if necessary. The digital peripherals are assigned Port pins in a pri-
ority order which is listed in Figure 19.3, with UART0 having the highest priority and CNVSTR2 having the lowest
priority.

19.1.1. Crossbar Pin Assignment and Allocation

The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in
the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in Figure 19.7, Figure 19.8, and Figure 19.9.
For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0 and RX0 pins will be mapped to P0.0 and
P0.1 respectively. Because UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when
UART0EN is set to a logic 1. If a digital peripheral's enable bits are not set to a logic 1, then its ports are not accessi-

Figure 19.3. Priority Crossbar Decode Table

PIN I/O 0

TX0

RX0

SCK

MISO

MOSI

NSS

NSS is not assigned to a port pin when the SPIis placed in 3-wire mode

SDA

G G G G G

SCL

G G G G G

TX1

G G G G G G G

RX1

G G G G G G G

CEX0

G G G G G G G G G

CEX1

G G G G G G G G G

CEX2

G G G G G G G G G

CEX3

G G G G G G G G G

CEX4

G G G G G G G G G

CEX5

G G G G G G G G G

ECI

G G G G G G G G G G G G G G G G G

ECI0E: XBR0.6

CP0

G G G G G G G G G G G G G G G G G G

CP0E: XBR0.7

CP1

G G G G G G G G G G G G G G G G G G G

CP1E: XBR1.0

G G G G G G G G G G G G G G G G G G G G

T0E: XBR1.1

/INT0

G G G G G G G G G G G G G G G G G G G G G

INT0E: XBR1.2

G G G G G G G G G G G G G G G G G G G G G G

T1E: XBR1.3

/INT1

G G G G G G G G G G G G G G G G G G G G G G G

INT1E: XBR1.4

G G G G G G G G G G G G G G G G G G G G G G G G

T2E: XBR1.5

T2EX

G G G G G G G G G G G G G G G G G G G G G G G G G

T2EXE: XBR1.6

G G G G G G G G G G G G G G G G G G G G G G G G G G

T4E: XBR2.3

T4EX

G G G G G G G G G G G G G G G G G G G G G G G G G G G

T4EXE: XBR2.4

/SYSCLK

G G G G G G G G G G G G G G G G G G G G G G G G G G G G

SYSCKE: XBR1.7

CNVSTR0

G G G G G G G G G G G G G G G G G G G G G G G G G G G G G

CNVSTE0: XBR2.0

CNVSTR2

G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G

CNVSTE2: XBR2.5

AIN

/A8

AIN

/A9

AIN

/A1

AIN

/A1

AIN

/A1

AIN

/A1

AIN

/A1

AIN

/A1

m/A0

m/A1

10m

/
A

11m

/
A

12m

/
A

13m

/
A

14m

/
A

15m

/
A

/
D

XBR2.2

XBR0.[5:3]

UART0EN:

SPI0EN:

Crossbar Register Bits

XBR0.2

XBR0.1

XBR0.0

SMB0EN:

AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L

Muxed Data/Non-muxed Data

UART1EN:

PCA0ME:

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ble at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when a serial
communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to assign TX0
to a Port pin without assigning RX0 as well. Each combination of enabled peripherals results in a unique device
pinout.

All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Purpose I/O
(GPIO) pins by reading and writing the associated Port Data registers (See Figure 19.10, Figure 19.12, Figure 19.15,
and Figure 19.17), a set of SFR's which are both byte- and bit-addressable. The output states of Port pins that are allo-
cated by the Crossbar are controlled by the digital peripheral that is mapped to those pins. Writes to the Port Data reg-
isters (or associated Port bits) will have no effect on the states of these pins.

A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of
whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution
of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SETB, and the bitwise
MOV write operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data
register, not the state of the Port pins themselves, which is read.

Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically configured in the
initialization code of the system before the peripherals themselves are configured. Once configured, the Crossbar reg-
isters are typically left alone.

Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE (XBR2.4) to a
logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are explicitly disabled in order
to prevent possible contention on the Port pins while the Crossbar registers and other registers which can
affect the device pinout are being written.

The output drivers on Crossbar-assigned input signals (like RX0, for example) are explicitly disabled; thus the values
of the Port Data registers and the PnMDOUT registers have no effect on the states of these pins.

19.1.2. Configuring the Output Modes of the Port Pins

The output drivers on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE (XBR2.4) to
a logic 1.

The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configura-
tion, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to GND, and
writing a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, writing a logic 0 to the
associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port
pin to assume a high-impedance state. The Open-Drain configuration is useful to prevent contention between devices
in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the
same physical wire (like the SDA signal on an SMBus connection).

The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated PnMDOUT regis-
ters (See Figure 19.11, Figure 19.14, Figure 19.16, and Figure 19.18). For example, a logic 1 in P3MDOUT.7 will
configure the output mode of P3.7 to Push-Pull; a logic 0 in P3MDOUT.7 will configure the output mode of P3.7 to
Open-Drain. All Port pins default to Open-Drain output.

The PnMDOUT registers control the output modes of the port pins regardless of whether the Crossbar has allocated
the Port pin for a digital peripheral or not. The exceptions to this rule are: the Port pins connected to SDA, SCL, RX0
(if UART0 is in Mode 0), and RX1 (if UART1 is in Mode 0) are always configured as Open-Drain outputs, regardless
of the settings of the associated bits in the PnMDOUT registers.

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19.1.3. Configuring Port Pins as Digital Inputs

A Port pin is configured as a digital input by setting its output mode to "Open-Drain" and writing a logic 1 to the
associated bit in the Port Data register. For example, P3.7 is configured as a digital input by setting P3MDOUT.7 to a
logic 0 and P3.7 to a logic 1.

If the Port pin has been assigned to a digital peripheral by the Crossbar and that pin functions as an input (for example
RX0, the UART0 receive pin), then the output drivers on that pin are automatically disabled.

19.1.4. Weak Pull-ups

By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about
100 k

) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the

Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is
driving a logic 0; that is, an output pin will not contend with its own pull-up device. The weak pull-up device can also
be explicitly disabled on any Port 1 pin by configuring the pin as an Analog Input, as described below.

19.1.5. Configuring Port 1 Pins as Analog Inputs

The pins on Port 1 can serve as analog inputs to the ADC2 analog MUX. A Port pin is configured as an Analog Input
by writing a logic 0 to the associated bit in the PnMDIN registers. All Port pins default to a Digital Input mode. Con-
figuring a Port pin as an analog input:

Disables the digital input path from the pin. This prevents additional power supply current from being

drawn when the voltage at the pin is near VDD / 2. A read of the Port Data bit will return a logic 0 regardless
of the voltage at the Port pin.
2.

Disables the weak pull-up device on the pin.

Causes the Crossbar to "skip over" the pin when allocating Port pins for digital peripherals.

Note that the output drivers on a pin configured as an Analog Input are not explicitly disabled. Therefore, the associ-
ated P1MDOUT bits of pins configured as Analog Inputs should explicitly be set to logic 0 (Open-Drain output
mode), and the associated Port1 Data bits should be set to logic 1 (high-impedance). Also note that it is not required
to configure a Port pin as an Analog Input in order to use it as an input to ADC2, however, it is strongly recom-
mended. See the ADC2 section in this datasheet for further information.

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C8051F124/5/6/7

19.1.6. External Memory Interface Pin Assignments

If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.5) should
be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Mem-
ory Interface is in Multiplexed mode, P0.5 (ALE). Figure 19.4 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Multiplexed mode. Figure 19.5 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Non-multiplexed mode.

If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Crossbar registers or the Port Data registers. The output configuration of
the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output
drivers on the Data Bus. See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP

XRAM" on page 199

for more information about the External Memory Interface.

Figure 19.4. Priority Crossbar Decode Table

EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN= 0xFF)

PIN I/O

TX0

RX0

SCK

MISO

MOSI

NSS

NSS is not assigned to a port pin when the SPIis placed in 3-wire mode

SDA

G G G

G G

SCL

G G

G G G

TX1

G G G

G G G G

RX1

G G

G G G G G

CEX0

G G G

G G G G G G

CEX1

G G

G G G G G G G

CEX2

G G G G G G G G

CEX3

G G G G G G G G

CEX4

G G G G G G G

G G

CEX5

G G G G G G

G G G

ECI

G G G G G

G G G G G G G G

G G G G

ECI0E: XBR0.6

CP0

G G G G G

G G G G G G G G

G G G G G

CP0E: XBR0.7

CP1

G G G G G

G G G G G G G G

G G G G G G

CP1E: XBR1.0

G G G G G

G G G G G G G G

G G G G G G G

T0E: XBR1.1

/INT0

G G G G G

G G G G G G G G

INT0E: XBR1.2

G G G G G

G G G G G G G G

G G G G G G G G G

T1E: XBR1.3

/INT1

G G G G G

G G G G G G G G

G G G G G G G G G G

INT1E: XBR1.4

G G G G G

G G G G G G G G

G G G G G G G G G G G

T2E: XBR1.5

T2EX

G G G G G

G G G G G G G G

G G G G G G G G G G G G

T2EXE: XBR1.6

G G G G G

G G G G G G G G

G G G G G G G G G G G G G

T4E: XBR2.3

T4EX

G G G G G

G G G G G G G G

G G G G G G G G G G G G G G

T4EXE: XBR2.4

/SYSCLK

G G G G G

G G G G G G G G

G G G G G G G G G G G G G G G

SYSCKE: XBR1.7

CNVSTR0

G G G G G

G G G G G G G G

G G G G G G G G G G G G G G G G

CNVSTE0: XBR2.0

CNVSTR2

G G G G G

G G G G G G G G

G G G G G G G G G G G G G G G G

CNVSTE2: XBR2.5

/RD

AIN1

/A8

AIN1

/A9

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

m/A0

m/A1

10m

/
A

11m

/
A

12m

/
A

13m

/
A

14m

/
A

15m

/
A

/
D

XBR2.2

XBR0.[5:3]

UART0EN:

SPI0EN:

Crossbar Register Bits

XBR0.2

XBR0.1

XBR0.0

SMB0EN:

AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L

Muxed Data/Non-muxed Data

UART1EN:

PCA0ME:

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Figure 19.5. Priority Crossbar Decode Table

PIN I/O 0

TX0

RX0

SCK

MISO

MOSI

NSS

NSS is not assigned to a port pin when the SPIis placed in 3-wire mode

SDA

G G G G

SCL

G G G

G G

TX1

G G G G

G G G

RX1

G G G

G G G G

CEX0

G G G G

G G G G G

CEX1

G G G

G G G G G G

CEX2

G G

G G G G G G G

CEX3

G G G G G G G G

CEX4

G G G G G G G G G

CEX5

G G G G G G G G G

ECI

G G G G G G

G G G G G G G G G G G

ECI0E: XBR0.6

CP0

G G G G G G

G G G G G G G G G G G G

CP0E: XBR0.7

CP1

G G G G G G

G G G G G G G G G G G G G

CP1E: XBR1.0

G G G G G G

G G G G G G G G G G G G G G

T0E: XBR1.1

/INT0

G G G G G G

G G G G G G G G G G G G G G G

INT0E: XBR1.2

G G G G G G

G G G G G G G G G G G G G G G G

T1E: XBR1.3

/INT1

G G G G G G

G G G G G G G G G G G G G G G G G

INT1E: XBR1.4

G G G G G G

G G G G G G G G G G G G G G G G G G

T2E: XBR1.5

T2EX

G G G G G G

G G G G G G G G G G G G G G G G G G G

T2EXE: XBR1.6

G G G G G G

G G G G G G G G G G G G G G G G G G G G

T4E: XBR2.3

T4EX

G G G G G G

G G G G G G G G G G G G G G G G G G G G G

T4EXE: XBR2.4

/SYSCLK

G G G G G G

G G G G G G G G G G G G G G G G G G G G G G

SYSCKE: XBR1.7

CNVSTR0

G G G G G G

G G G G G G G G G G G G G G G G G G G G G G G

CNVSTE0: XBR2.0

CNVSTR2

G G G G G G

G G G G G G G G G G G G G G G G G G G G G G G G

CNVSTE2: XBR2.5

/RD

AIN1

/A8

AIN1

/A9

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

m/A0

m/A1

10m

/
A

11m

/
A

12m

/
A

13m

/
A

14m

/
A

15m

/
A

/
D

XBR2.2

XBR0.[5:3]

UART0EN:

SPI0EN:

Crossbar Register Bits

XBR0.2

XBR0.1

XBR0.0

SMB0EN:

AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L

Muxed Data/Non-muxed Data

UART1EN:

PCA0ME:

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C8051F124/5/6/7

19.1.7. Crossbar Pin Assignment Example

In this example (Figure 19.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, /
INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in Multiplexed
mode and to appear on the Low ports. Further, we configure P1.2, P1.3, and P1.4 for Analog Input mode so that the
voltages at these pins can be measured by ADC2. The configuration steps are as follows:

XBR0, XBR1, and XBR2 are set such that UART0EN = 1, SMB0EN = 1, INT0E = 1, INT1E = 1, and

EMIFLE = 1. Thus: XBR0 = 0x05, XBR1 = 0x14, and XBR2 = 0x02.
2.

We configure the External Memory Interface to use Multiplexed mode and to appear on the Low ports.

PRTSEL = 0, EMD2 = 0.
3.

We configure the desired Port 1 pins to Analog Input mode by setting P1MDIN to 0xE3 (P1.4, P1.3, and

P1.2 are Analog Inputs, so their associated P1MDIN bits are set to logic 0).
4.

We enable the Crossbar by setting XBARE = 1: XBR2 = 0x42.
-

UART0 has the highest priority, so P0.0 is assigned to TX0, and P0.1 is assigned to RX0.

The SMBus is next in priority order, so P0.2 is assigned to SDA, and P0.3 is assigned to SCL.

UART1 is next in priority order, so P0.4 is assigned to TX1. Because the External Memory Inter-
face is selected on the lower Ports, EMIFLE = 1, which causes the Crossbar to skip P0.6 (/RD) and
P0.7 (/WR). Because the External Memory Interface is configured in Multiplexed mode, the Cross-
bar will also skip P0.5 (ALE). RX1 is assigned to the next non-skipped pin, which in this case is
P1.0.

/I NT0 is next in priority order, so it is assigned to P1.1.

P1MDIN is set to 0xE3, which configures P1.2, P1.3, and P1.4 as Analog Inputs, causing the
Crossbar to skip these pins.

/I NT1 is next in priority order, so it is assigned to the next non-skipped pin, which is P1.5.

The External Memory Interface will drive Ports 2 and 3 (denoted by red dots in Figure 19.6) during
the execution of an off-chip MOVX instruction.

We set the UART0 TX pin (TX0, P0.0) and UART1 TX pin (TX1, P0.4) outputs to Push-Pull by setting

P0MDOUT = 0x11.
6.

We configure all EMIF-controlled pins to push-pull output mode by setting P0MDOUT |= 0xE0;

P2MDOUT = 0xFF; P3MDOUT = 0xFF.
7.

We explicitly disable the output drivers on the 3 Analog Input pins by setting P1MDOUT = 0x00 (con-

figure outputs to Open-Drain) and P1 = 0xFF (a logic 1 selects the high-impedance state).

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Figure 19.6. Crossbar Example:

(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN= 0xE3;

PIN I/O 0

TX0

RX0

SCK

MISO

MOSI

NSS

SDA

G G

SCL

G G

TX1

G G

RX1

G G

G G G

CEX0

G G G

G G

G G G

CEX1

G G

G G G

G G

CEX2

G G

G G G

CEX3

G G

G G G

G G G G

CEX4

G G

G G G

G G G G G

CEX5

G G

G G G

G G G G G G

ECI

G G G G G

G G

G G G

G G G G G G G

ECI0E: XBR0.6

CP0

G G G G G

G G

G G G

G G G G G G G G

CP0E: XBR0.7

CP1

G G G G G

G G

G G G

G G G G G G G G G

CP1E: XBR1.0

G G G G G

G G

G G G

G G G G G G G G G G

T0E: XBR1.1

/INT0

G G G G G

G G G

G G G G G G G G G G G

INT0E: XBR1.2

G G G G G

G G

G G G

G G G G G G G G G G G G

T1E: XBR1.3

/INT1

G G G G G

G G

G G G G G G G G G G G G G

INT1E: XBR1.4

G G G G G

G G

G G G

G G G G G G G G G G G G G G

T2E: XBR1.5

T2EX

G G G G G

G G

G G G

G G G G G G G G G G G G G G G

T2EXE: XBR1.6

G G G G G

G G

G G G

G G G G G G G G G G G G G G G G

T4E: XBR2.3

T4EX

G G G G G

G G

G G G

G G G G G G G G G G G G G G G G

T4EXE: XBR2.4

/SYSCLK

G G G G G

G G

G G G

G G G G G G G G G G G G G G G G

SYSCKE: XBR1.7

CNVSTR0

G G G G G

G G

G G G

G G G G G G G G G G G G G G G G

CNVSTE0: XBR2.0

CNVSTR2

G G G G G

G G

G G G

G G G G G G G G G G G G G G G G

CNVSTE2: XBR2.5

/RD

AIN1

/A8

AIN1

/A9

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

AIN1

/A1

m/A0

m/A1

10m

/
A

11m

/
A

12m

/
A

13m

/
A

14m

/
A

15m

/
A

/
D

XBR2.2

XBR0.[5:3]

UART0EN:

SPI0EN:

Crossbar Register Bits

XBR0.2

XBR0.1

XBR0.0

SMB0EN:

AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L

Muxed Data/Non-muxed Data

UART1EN:

PCA0ME:

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C8051F124/5/6/7

Figure 19.7. XBR0: Port I/O Crossbar Register 0

Bit7:

CP0E: Comparator 0 Output Enable Bit.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.

Bit6:

ECI0E: PCA0 External Counter Input Enable Bit.
0: PCA0 External Counter Input unavailable at Port pin.
1: PCA0 External Counter Input (ECI0) routed to Port pin.

Bits5-3:

PCA0ME: PCA0 Module I/O Enable Bits.
000: All PCA0 I/O unavailable at port pins.
001: CEX0 routed to port pin.
010: CEX0, CEX1 routed to 2 port pins.
011: CEX0, CEX1, and CEX2 routed to 3 port pins.
100: CEX0, CEX1, CEX2, and CEX3 routed to 4 port pins.
101: CEX0, CEX1, CEX2, CEX3, and CEX4 routed to 5 port pins.
110: CEX0, CEX1, CEX2, CEX3, CEX4, and CEX5 routed to 6 port pins.

Bit2:

UART0EN: UART0 I/O Enable Bit.
0: UART0 I/O unavailable at Port pins.
1: UART0 TX routed to P0.0, and RX routed to P0.1.

Bit1:

SPI0EN: SPI0 Bus I/O Enable Bit.
0: SPI0 I/O unavailable at Port pins.
1: SPI0 SCK, MISO, MOSI, and NSS routed to 4 Port pins. Note that the NSS signal is not assigned
to a port pin if the SPIis in 3-wire mode. See Section "

18. EXTERNAL DATA MEMORY INTER-

FACE AND ON-CHIP XRAM

" on page

199

for more information.

Bit0:

SMB0EN: SMBus0 Bus I/O Enable Bit.
0: SMBus0 I/O unavailable at Port pins.
1: SMBus0 SDA and SCL routed to 2 Port pins.

R/W

Reset Value

CP0E

ECI0E

PCA0ME

UART0EN

SPI0EN

SMB0EN

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xE1
F

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C8051F124/5/6/7

Figure 19.8. XBR1: Port I/O Crossbar Register 1

Bit7:

SYSCKE: /SYSCLK Output Enable Bit.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. divide factor is determined by the
CLKDIV1-0 bits in register CLKSEL (See

Section "15. OSCILLATORS" on page 173

Bit6:

T2EXE: T2EX Input Enable Bit.
0: T2EX unavailable at Port pin.
1: T2EX routed to Port pin.

Bit5:

T2E: T2 Input Enable Bit.
0: T2 unavailable at Port pin.
1: T2 routed to Port pin.

Bit4:

INT1E: /INT1 Input Enable Bit.
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port pin.

Bit3:

T1E: T1 Input Enable Bit.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.

Bit2:

INT0E: /INT0 Input Enable Bit.
0: /INT0 unavailable at Port pin.
1: /INT0 routed to Port pin.

Bit1:

T0E: T0 Input Enable Bit.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.

Bit0:

CP1E: CP1 Output Enable Bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.

R/W

Reset Value

SYSCKE

T2EXE

T2E

INT1E

T1E

INT0E

T0E

CP1E

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xE2
F

Page 226

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.9. XBR2: Port I/O Crossbar Register 2

Bit7:

WEAKPUD: Weak Pull-Up Disable Bit.
0: Weak pull-ups globally enabled.
1: Weak pull-ups globally disabled.

Bit6:

XBARE: Crossbar Enable Bit.
0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.
1: Crossbar enabled.

Bit5:

CNVST2E: External Convert Start 2 Input Enable Bit.
0: CNVSTR2 unavailable at Port pin.
1: CNVSTR2 routed to Port pin.

Bit4:

T4EXE: T4EX Input Enable Bit.
0: T4EX unavailable at Port pin.
1: T4EX routed to Port pin.

Bit3:

T4E: T4 Input Enable Bit.
0: T4 unavailable at Port pin.
1: T4 routed to Port pin.

Bit2:

UART1E: UART1 I/O Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX and RX routed to 2 Port pins.

Bit1:

EMIFLE: External Memory Interface Low-Port Enable Bit.
0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port latches.
1: If EMI0CF.4 = `0' (External Memory Interface is in Multiplexed mode)

P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) are `skipped' by the Crossbar and their output
states are determined by the Port latches and the External Memory Interface.

1: If EMI0CF.4 = `1' (External Memory Interface is in Non-multiplexed mode)

P0.7 (/WR) and P0.6 (/RD) are `skipped' by the Crossbar and their output states are
determined by the Port latches and the External Memory Interface.

Bit0:

CNVST0E: ADC0 External Convert Start Input Enable Bit.

R/W

Reset Value

WEAKPUD XBARE CNVST2E

T4EXE

T4E

UART1E

EMIFLE

CNVST0E 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xE3
F

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.10. P0: Port0 Data Register

Bits7-0:

P0.[7:0]: Port0 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P0MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.

Note: P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) can be driven by the External Data Memory Interface.
See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM" on

page 199

for more information. See also Figure 19.9 for information about configuring the Crossbar

for External Memory accesses.

R/W

Reset Value

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x80
All Pages

Figure 19.11. P0MDOUT: Port0 Output Mode Register

Bits7-0:

P0MDOUT.[7:0]: Port0 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

Note:

SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA4
F

Page 228

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.12. P1: Port1 Data Register

Bits7-0:

P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.

Notes:
1.

P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are `skipped' by the
Crossbar assignment process and their digital input paths are disabled, depending on P1MDIN (See
Figure 19.13). Note that in analog mode, the output mode of the pin is determined by the Port 1 latch
and P1MDOUT (Figure 19.14). See

Section "7. ADC2 (8-Bit ADC)" on page 85

for more informa-

tion about ADC2.

P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM"

on page 199

for more information about the External Memory Interface.

R/W

Reset Value

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x90
All Pages

Figure 19.13. P1MDIN: Port1 Input Mode Register

Bits7-0:

P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from the
Port bit will always return `0'). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic level at
the Pin. When configured as a digital input, the state of the weak pull-up for the port pin is determined
by the WEAKPUD bit (XBR2.7, see Figure 19.9).

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xAD
F

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.14. P1MDOUT: Port1 Output Mode Register

Bits7-0:

P1MDOUT.[7:0]: Port1 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

Note:

SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA5
F

Figure 19.15. P2: Port2 Data Register

Bits7-0:

P2.[7:0]: Port2 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P2MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P2.n pin is logic low.
1: P2.n pin is logic high.

Note:

P2.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See

Section "18. EXTERNAL DATA MEM-

ORY INTERFACE AND ON-CHIP XRAM" on page 199

for more information about the External

Memory Interface.

R/W

Reset Value

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xA0
All Pages

Page 230

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.16. P2MDOUT: Port2 Output Mode Register

Bits7-0:

P2MDOUT.[7:0]: Port2 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

Note:

SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA6
F

Figure 19.17. P3: Port3 Data Register

Bits7-0:

P3.[7:0]: Port3 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.

Note:

P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See

Section "18. EXTERNAL DATA MEMORY INTER-

FACE AND ON-CHIP XRAM" on page 199

for more information about the External Memory

Interface.

R/W

Reset Value

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xB0
All Pages

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

19.2.

Ports 4 through 7 (C8051F120/2/4/6 only)

All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the
associated Port Data registers (See Figure 19.19, Figure 19.21, Figure 19.23, and Figure 19.25), a set of SFR's which
are both bit and byte-addressable.

19.2.1. Configuring Ports which are not Pinned Out

Although P4, P5, P6, and P7 are not brought out to pins on the C8051F121/3/5/7 devices, the Port Data registers are
still present and can be used by software. Because the digital input paths also remain active, it is recommended that
these pins not be left in a `floating' state in order to avoid unnecessary power dissipation arising from the inputs float-
ing to non-valid logic levels. This condition can be prevented by any of the following:

Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.

Configure the output modes of P4, P5, P6, and P7 to "Push-Pull" by writing PnMDOUT = 0xFF.

Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data registers: P4 =

0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.

19.2.2. Configuring the Output Modes of the Port Pins

The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configura-
tion, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1
will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the
Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high-
impedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the
Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire.

The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective PnMDOUT Out-
put Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding port pin (see Figure 19.20,
Figure 19.22, Figure 19.24, and Figure 19.26). For example, to place Port pin 4.3 in push-pull mode (digital output),
set P4MDOUT.3 to logic 1. All port pins default to open-drain mode upon device reset.

Figure 19.18. P3MDOUT: Port3 Output Mode Register

Bits7-0:

P2MDOUT.[7:0]: Port3 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA7
F

Page 232

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C8051F120/1/2/3
C8051F124/5/6/7

19.2.3. Configuring Port Pins as Digital Inputs

A Port pin is configured as a digital input by setting its output mode to "Open-Drain" and writing a logic 1 to the
associated bit in the Port Data register. For example, P7.7 is configured as a digital input by setting P7MDOUT.7 to a
logic 0 and P7.7 to a logic 1.

19.2.4. Weak Pull-ups

By default, each Port pin has an internal weak pull-up device enabled which provides a resistive connection (about
100 k

) between the pin and VDD. The weak pull-up devices can be globally disabled by writing a logic 1 to the

Weak Pull-up Disable bit, (WEAKPUD, XBR2.7). The weak pull-up is automatically deactivated on any pin that is
driving a logic 0; that is, an output pin will not contend with its own pull-up device.

19.2.5. External Memory Interface

If the External Memory Interface (EMIF) is enabled on the High ports (Ports 4 through 7), EMIFLE (XBR2.5) should
be set to a logic 0.

If the External Memory Interface is enabled on the High ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Port Data registers. The output configuration of the Port pins is not
affected by the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus
during the MOVX execution. See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP

XRAM" on page 199

for more information about the External Memory Interface.

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.19. P4: Port4 Data Register

Bits7-0:

P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P4MDOUT.n bit = 0). See Figure 19.20.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.

Note: P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM" on

page 199

for more information.

R/W

Reset Value

P4.7

P4.6

P4.5

P4.4

P4.3

P4.2

P4.1

P4.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xC8
F

Figure 19.20. P4MDOUT: Port4 Output Mode Register

Bits7-0:

P4MDOUT.[7:0]: Port4 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9C
F

Page 234

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.21. P5: Port5 Data Register

Bits7-0:

P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P5MDOUT bit = 0). See Figure 19.22.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.

Note:

P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See

Section "18. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM"

on page 199

for more information about the External Memory Interface.

R/W

Reset Value

P5.7

P5.6

P5.5

P5.4

P5.3

P5.2

P5.1

P5.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xD8
F

Figure 19.22. P5MDOUT: Port5 Output Mode Register

Bits7-0:

P5MDOUT.[7:0]: Port5 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9D
F

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.23. P6: Port6 Data Register

Bits7-0:

P6.[7:0]: Port6 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P6MDOUT bit = 0). See Figure 19.24.
Read - Returns states of I/O pins.
0: P6.n pin is logic low.
1: P6.n pin is logic high.

Note:

P6.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Multiplexed
mode, or as Address[7:0] in Non-multiplexed mode). See

Section "18. EXTERNAL DATA MEM-

ORY INTERFACE AND ON-CHIP XRAM" on page 199

for more information about the External

Memory Interface.

R/W

Reset Value

P6.7

P6.6

P6.5

P6.4

P6.3

P6.2

P6.1

P6.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xE8
F

Figure 19.24. P6MDOUT: Port6 Output Mode Register

Bits7-0:

P6MDOUT.[7:0]: Port6 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9E
F

Page 236

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 19.25. P7: Port7 Data Register

Bits7-0:

P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P7MDOUT bit = 0). See Figure 19.26.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.

Note:

P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or
as D[7:0] in Non-multiplexed mode). See

Section "18. EXTERNAL DATA MEMORY INTER-

FACE AND ON-CHIP XRAM" on page 199

for more information about the External Memory

Interface.

R/W

Reset Value

P7.7

P7.6

P7.5

P7.4

P7.3

P7.2

P7.1

P7.0

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xF8
F

Figure 19.26. P7MDOUT: Port7 Output Mode Register

Bits7-0:

P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.

Note:

SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always
configured as Open-Drain when they appear on Port pins.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9F
F

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

20.

SYSTEM MANAGEMENT BUS / I

C BUS (SMBUS0)

The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage-

ment Bus Specification, version 1.1, and compatible with the I

C serial bus. Reads and writes to the interface by the

system controller are byte oriented with the SMBus0 interface autonomously controlling the serial transfer of the
data. A method of extending the clock-low duration is available to accommodate devices with different speed capa-
bilities on the same bus.

SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0 provides
control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP
control and generation.

Figure 20.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between 3.0 V and
5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock)

Figure 20.1. SMBus0 Block Diagram

SFR Bus

Data Path

Control

SFR Bus

Write to

SMB0DAT

SMBUS CONTROL LOGIC

Read

SMB0DAT

SMB0ADR

S
L
V
6

G
C

S
L
V
5

S
L
V
4

S
L
V
3

S
L
V
2

S
L
V
1

S
L
V
0

C
R
O

S
S
B
A

Clock Divide

Logic

SYSCLK

SMB0CR

C
R

SCL

FILTER

SDA

Control

0000000b

7 MSBs

SMB0DAT

SMB0CN

S
T
A

A
A

F
T
E

O
E

E
N
S

B
U
S
Y

S
T

SMB0STA

S
T
A
4

S
T
A
3

S
T
A
2

S
T
A
1

S
T
A
0

SCL

Control

Status Generation

Arbitration
SCL Synchronization

SCL Generation (Master Mode)
IRQ Generation

S
T
A
5

S
T
A
6

S
T
A
7

SMBUS

IRQ

Interrupt
Request

PortI/O

SDA

FILTER

Page 238

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C8051F120/1/2/3
C8051F124/5/6/7

and SDA (serial data) lines must be connected to a positive power supply voltage through a pull-up resistor or similar
circuit. Every device connected to the bus must have an open-drain or open-collector output for both the SCL and
SDA lines, so that both are pulled high when the bus is free. The maximum number of devices on the bus is limited
only by the requirement that the rise and fall times on the bus will not exceed 300 ns and 1000 ns, respectively.

20.1.

Supporting Documents

It is assumed the reader is familiar with or has access to the following supporting documents:

The I

C-bus and how to use it (including specifications), Philips Semiconductor.

The I

C-Bus Specification -- Version 2.0, Philips Semiconductor.

System Management Bus Specification -- Version 1.1, SBS Implementers Forum.

20.2.

SMBus Protocol

Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver
(WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device ini-
tiates both types of data transfers and provides the serial clock pulses on SCL. Note: multiple master devices on the
same bus are supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration
scheme is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the master in a system; any device who transmits a START and a slave address becomes the master for that
transfer.

A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit slave
address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a
master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see Figure 20.3). If the receiving
device does not ACK, the transmitting device will read a "not acknowledge" (NACK), which is a high SDA during a
high SCL.

The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to logic 1 to
indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.

All transactions are initiated by a master, with one or more addressed slave devices as the target. The master gener-
ates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE opera-

Figure 20.2. Typical SMBus Configuration

VDD = 5V

Master
Device

Slave

Device 1

Slave

Device 2

VDD = 3V

VDD = 5V

VDD = 3V

SDA

SCL

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tion from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at
the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the
end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction
and free the bus. Figure 20.3 illustrates a typical SMBus transaction.

20.2.1. Arbitration

A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA
lines remain high for a specified time (see

Section 20.2.4

). In the event that two or more devices attempt to begin a

transfer at the same time, an arbitration scheme is employed to force one master to give up the bus. The master
devices continue transmitting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-
drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and give up the bus. The
winning master continues its transmission without interruption; the losing master becomes a slave and receives the
rest of the transfer. This arbitration scheme is non-destructive: one device always wins, and no data is lost.

20.2.2. Clock Low Extension

SMBus provides a clock synchronization mechanism, similar to I

C, which allows devices with different speed capa-

bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to
communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period,
effectively decreasing the serial clock frequency.

20.2.3. SCL Low Timeout

If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas-
ter cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies
that devices participating in a transfer must detect any clock cycle held low longer than 25 ms as a "timeout" condi-
tion. Devices that have detected the timeout condition must reset the communication no later than 10 ms after detect-
ing the timeout condition.

20.2.4. SCL High (SMBus Free) Timeout

The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus is desig-
nated as free. If an SMBus device is waiting to generate a Master START, the START will be generated following the
bus free timeout.

SLA6

SDA

SLA5-0

R/W

D6-0

SCL

Slave Address + R/W

Dat a Byt e

START

ACK

NACK

STOP

Figure 20.3. SMBus Transaction

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20.3.

SMBus Transfer Modes

The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the interface
will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave
Receiver. See Table 20.1 for transfer mode status decoding using the SMB0STA status register. The following mode
descriptions illustrate an interrupt-driven SMBus0 application; SMBus0 may alternatively be operated in polled
mode.

20.3.1. Master Transmitter Mode

Serial data is transmitted on SDA while the serial clock is output on SCL. SMBus0 generates a START condition and
then transmits the first byte containing the address of the target slave device and the data direction bit. In this case the
data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface transmits one or
more bytes of serial data, waiting for an acknowledge (ACK) from the slave after each byte. To indicate the end of the
serial transfer, SMBus0 generates a STOP condition.

20.3.2. Master Receiver Mode

Serial data is received on SDA while the serial clock is output on SCL. The SMBus0 interface generates a START
followed by the first data byte containing the address of the target slave and the data direction bit. In this case the data
direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives serial data from
the slave and generates the clock on SCL. After each byte is received, SMBus0 generates an ACK or NACK depend-
ing on the state of the AA bit in register SMB0CN. SMBus0 generates a STOP condition to indicate the end of the
serial transfer.

Data Byte

SLA

S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address

Received by SMBus
Interface

Transmitted by
SMBus Interface

Interrupt

Figure 20.4. Typical Master Transmitter Sequence

Data Byte

SLA

S = START
P = STOP
A = ACK
N = NACK
R = READ
SLA = Slave Address

Received by SMBus
Interface

Transmitted by
SMBus Interface

Interrupt

Figure 20.5. Typical Master Receiver Sequence

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20.3.3. Slave Transmitter Mode

Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will also ACK if the general call
address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the
data direction bit (R/W) will be logic 1 to indicate a "READ" operation. The SMBus0 interface receives the clock on
SCL and transmits one or more bytes of serial data, waiting for an ACK from the master after each byte. SMBus0
exits slave mode after receiving a STOP condition from the master.

20.3.4. Slave Receiver Mode

Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START
followed by data byte containing the slave address and direction bit. If the received slave address matches the address
held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if the general call address
(0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to logic 1. In this case the data direc-
tion bit (R/W) will be logic 0 to indicate a "WRITE" operation. The SMBus0 interface receives one or more bytes of
serial data; after each byte is received, the interface transmits an ACK or NACK depending on the state of the AA bit
in SMB0CN. SMBus0 exits Slave Receiver Mode after receiving a STOP condition from the master.

SLA

Data Byte

S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address

Received by SMBus
Interface

Transmitted by
SMBus Interface

Interrupt

Figure 20.6. Typical Slave Transmitter Sequence

SLA

Data Byte

S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address

Received by SMBus
Interface

Transmitted by
SMBus Interface

Interrupt

Figure 20.7. Typical Slave Receiver Sequence

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20.4.

SMBus Special Function Registers

The SMBus0 serial interface is accessed and controlled through five SFR's: SMB0CN Control Register, SMB0CR
Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The
five special function registers related to the operation of the SMBus0 interface are described in the following sec-
tions.

20.4.1. Control Register

The SMBus0 Control register SMB0CN is used to configure and control the SMBus0 interface. All of the bits in the
register can be read or written by software. Two of the control bits are also affected by the SMBus0 hardware. The
Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs.
It can only be cleared by software. The Stop flag (STO, SMB0CN.4) is set to logic 1 by software. It is cleared to logic
0 by hardware when a STOP condition is detected on the bus.

Setting the ENSMB flag to logic 1 enables the SMBus0 interface. Clearing the ENSMB flag to logic 0 disables the
SMBus0 interface and removes it from the bus. Momentarily clearing the ENSMB flag and then resetting it to logic 1
will reset SMBus0 communication. However, ENSMB should not be used to temporarily remove a device from the
bus since the bus state information will be lost. Instead, the Assert Acknowledge (AA) flag should be used to tempo-
rarily remove the device from the bus (see description of AA flag below).

Setting the Start flag (STA, SMB0CN.5) to logic 1 will put SMBus0 in a master mode. If the bus is free, SMBus0 will
generate a START condition. If the bus is not free, SMBus0 waits for a STOP condition to free the bus and then gen-
erates a START condition after a 5 µs delay per the SMB0CR value (In accordance with the SMBus protocol, the
SMBus0 interface also considers the bus free if the bus is idle for 50 µs and no STOP condition was recognized). If
STA is set to logic 1 while SMBus0 is in master mode and one or more bytes have been transferred, a repeated
START condition will be generated.

When the Stop flag (STO, SMB0CN.4) is set to logic 1 while the SMBus0 interface is in master mode, the interface
generates a STOP condition. In a slave mode, the STO flag may be used to recover from an error condition. In this
case, a STOP condition is not generated on the bus, but the SMBus hardware behaves as if a STOP condition has been
received and enters the "not addressed" slave receiver mode. Note that this simulated STOP will not cause the bus to
appear free to SMBus0. The bus will remain occupied until a STOP appears on the bus or a Bus Free Timeout occurs.
Hardware automatically clears the STO flag to logic 0 when a STOP condition is detected on the bus.

The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by hardware when the SMBus0 interface enters one of 27
possible states. If interrupts are enabled for the SMBus0 interface, an interrupt request is generated when the SI flag
is set. The SIflag must be cleared by software.

Important Note: If SI is set to logic 1 while the SCL line is low, the clock-low period of the serial clock will be
stretched and the serial transfer is suspended until SIis cleared to logic 0. A high level on SCL is not affected by the
setting of the SIflag.

The Assert Acknowledge flag (AA, SMB0CN.2) is used to set the level of the SDA line during the acknowledge
clock cycle on the SCL line. Setting the AA flag to logic 1 will cause an ACK (low level on SDA) to be sent during
the acknowledge cycle if the device has been addressed. Setting the AA flag to logic 0 will cause a NACK (high level
on SDA) to be sent during acknowledge cycle. After the transmission of a byte in slave mode, the slave can be tempo-
rarily removed from the bus by clearing the AA flag. The slave's own address and general call address will be
ignored. To resume operation on the bus, the AA flag must be reset to logic 1 to allow the slave's address to be recog-
nized.

Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL
goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if SMBus0 is waiting to

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generate a START, it will do so after this timeout. The bus free period should be less than 50 µs (see Figure 20.9,
SMBus0 Clock Rate Register).

When the TOE bit in SMB0CN is set to logic 1, Timer 3 is used to detect SCL low timeouts. If Timer 3 is enabled
(see

Section "24.2. Timer 2, Timer 3, and Timer 4" on page 293

), Timer 3 is forced to reload when SCL is high,

and forced to count when SCL is low. With Timer 3 enabled and configured to overflow after 25 ms (and TOE set), a
Timer 3 overflow indicates a SCL low timeout; the Timer 3 interrupt service routine can then be used to reset
SMBus0 communication in the event of an SCL low timeout.

Figure 20.8. SMB0CN: SMBus0 Control Register

Bit7:

BUSY: Busy Status Flag.
0: SMBus0 is free
1: SMBus0 is busy

Bit6:

ENSMB: SMBus Enable.
This bit enables/disables the SMBus serial interface.
0: SMBus0 disabled.
1: SMBus0 enabled.

Bit5:

STA: SMBus Start Flag.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the bus is not
free, the START is transmitted after a STOP is received.) If STA is set after one or more bytes have
been transmitted or received and before a STOP is received, a repeated START condition is transmit-
ted.

Bit4:

STO: SMBus Stop Flag.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condition is
received, hardware clears STO to logic 0. If both STA and STO are set, a STOP condition is transmit-
ted followed by a START condition. In slave mode, setting the STO flag causes SMBus to behave as
if a STOP condition was received.

Bit3:

SI: SMBus Serial Interrupt Flag.
This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code 0xF8 does
not cause SIto be set.) When the SIinterrupt is enabled, setting this bit causes the CPU to vector to
the SMBus interrupt service routine. This bit is not automatically cleared by hardware and must be
cleared by software.

Bit2:

AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL line.
0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle.
1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle.

Bit1:

FTE: SMBus Free Timer Enable Bit
0: No timeout when SCL is high
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.

Bit0:

TOE: SMBus Timeout Enable Bit
0: No timeout when SCL is low.
1: Timeout when SCL low time exceeds limit specified by Timer 3, if enabled.

R/W

Reset Value

BUSY

ENSMB

STA

STO

SIAA

FTE

TOE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xC0
0

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20.4.2. Clock Rate Register

Figure 20.9. SMB0CR: SMBus0 Clock Rate Register

Bits7-0:

SMB0CR.[7:0]: SMBus0 Clock Rate Preset
The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The
8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and
when it rolls over to 0x00, the SCL logic state toggles.

The SMB0CR setting should be bounded by the following equation , where SMB0CR is the unsigned
8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in MHz:

The resulting SCL signal high and low times are given by the following equations, where SYSCLK is
the system clock frequency in Hz:

Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the following
equation:

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xCF
0

SMB0CR

288

0.85

SYSCLK

----------------------

1.125

LOW

256

SMB0CR

(

)

SYSCLK

HIGH

258

SMB0CR

(

)

SYSCLK

625ns

BFT

256

SMB0CR

(

)

SYSCLK

--------------------------------------------------------------

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20.4.3. Data Register

The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Software can read or write to this register while the SIflag is set to logic 1; software should not attempt to access the
SMB0DAT register when the SMBus is enabled and the SIflag reads logic 0 since the hardware may be in the pro-
cess of shifting a byte of data in or out of the register.

Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.
Therefore, SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transi-
tion from master transmitter to slave receiver is made with the correct data in SMB0DAT.

20.4.4. Address Register

The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the recognition of the
general call address (0x00). If Bit0 is set to logic 1, the general call address will be recognized. Otherwise, the general
call address is ignored. The contents of this register are ignored when SMBus0 is operating in master mode.

Figure 20.10. SMB0DAT: SMBus0 Data Register

Bits7-0:

SMB0DAT: SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial interface or a
byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to
this register whenever the SIserial interrupt flag (SMB0CN.3) is set to logic 1. When the SIflag is
not set, the system may be in the process of shifting data and the CPU should not attempt to access
this register.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xC2
0

Figure 20.11. SMB0ADR: SMBus0 Address Register

Bits7-1:

SLV6-SLV0: SMBus0 Slave Address.
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when operating as a
slave transmitter or slave receiver. SLV6 is the most significant bit of the address and corresponds to
the first bit of the address byte received.

Bit0:

GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.

R/W

Reset Value

SLV6

SLV5

SLV4

SLV3

SLV2

SLV1

SLV0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xC3
0

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20.4.5. Status Register

The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There
are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of the
status code vary while the three least-significant bits of a valid status code are fixed at zero when SI= `1'. Therefore,
all possible status codes are multiples of eight. This facilitates the use of status codes in software as an index used to
branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive ser-
vice routine).

For the purposes of user software, the contents of the SMB0STA register is only defined when the SIflag is logic 1.
Software should never write to the SMB0STA register; doing so will yield indeterminate results. The 28 SMBus0
states, along with their corresponding status codes, are given in Table 1.1.

Figure 20.12. SMB0STA: SMBus0 Status Register

Bits7-3:

STA7-STA3: SMBus0 Status Code.
These bits contain the SMBus0 Status Code. There are 28 possible status codes; each status code cor-
responds to a single SMBus state. A valid status code is present in SMB0STA when the SIflag
(SMB0CN.3) is set to logic 1. The content of SMB0STA is not defined when the SIflag is logic 0.
Writing to the SMB0STA register at any time will yield indeterminate results.

Bits2-0:

STA2-STA0: The three least significant bits of SMB0STA are always read as logic 0 when the SIflag
is logic 1.

R/W

Reset Value

STA7

STA6

STA5

STA4

STA3

STA2

STA1

STA0

11111000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xC1
0

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Table 20.1. SMB0STA Status Codes and States

Mode

Status

Code

SMBus State

Typical Action

0x08

START condition transmitted.

Load SMB0DAT with Slave Address +
R/W. Clear STA.

0x10

Repeated START condition transmitted.

Load SMB0DAT with Slave Address +
R/W. Clear STA.

Maste

r
an

smi

t
ter

0x18

Slave Address + W transmitted. ACK
received.

Load SMB0DAT with data to be transmit-
ted.

0x20

Slave Address + W transmitted. NACK
received.

Acknowledge poll to retry. Set STO +
STA.

0x28

Data byte transmitted. ACK received.

1) Load SMB0DAT with next byte, OR
2) SetSTO, OR
3) Clear STO then set STA for repeated
START.

0x30

Data byte transmitted. NACK received.

1) Retry transfer OR
2) SetSTO.

0x38

Arbitration Lost.

Save current data.

Master

Rece

i
v

0x40

Slave Address + R transmitted. ACK received.

If only receiving one byte, clear AA (send
NACK after received byte). Wait for
received data.

0x48

Slave Address + R transmitted. NACK
received.

Acknowledge poll to retry. Set STO +
STA.

0x50

Data byte received. ACK transmitted.

Read SMB0DAT. Wait for next byte. If
nextbyte is lastbyte, clear AA.

0x58

Data byte received. NACK transmitted.

Set STO.

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ver

0x60

Own slave address + W received. ACK trans-
mitted.

Waitfor data.

0x68

Arbitration lost in sending SLA + R/W as mas-
ter. Own address + W received. ACK transmit-
ted.

Save currentdata for retry when bus is
free. Waitfor data.

0x70

General call address received. ACK transmit-
ted.

Waitfor data.

0x78

Arbitration lost in sending SLA + R/W as mas-
ter. General call address received. ACK trans-
mitted.

Save currentdata for retry when bus is
free.

0x80

Data byte received. ACK transmitted.

Read SMB0DAT. Wait for next byte or
STOP.

0x88

Data byte received. NACK transmitted.

Set STO to reset SMBus.

0x90

Data byte received after general call address.
ACK transmitted.

Read SMB0DAT. Waitfor nextbyte or
STOP.

0x98

Data byte received after general call address.
NACK transmitted.

SetSTO to resetSMBus.

0xA0

STOP or repeated START received.

No action necessary.

l
av

i
tt

0xA8

Own address + R received. ACK transmitted.

Load SMB0DAT with data to transmit.

0xB0

Arbitration lost in transmitting SLA + R/W as
master. Own address + R received. ACK
transmitted.

Save currentdata for retry when bus is
free. Load SMB0DAT with data to trans-
mit.

0xB8

Data byte transmitted. ACK received.

Load SMB0DAT with data to transmit.

0xC0

Data byte transmitted. NACK received.

Wait for STOP.

0xC8

Last data byte transmitted (AA=0). ACK
received.

SetSTO to resetSMBus.

Slave

0xD0

SCL Clock High Timer per SMB0CR timed out

Set STO to reset SMBus.

All

0x00

Bus Error (illegal START or STOP)

SetSTO to resetSMBus.

0xF8

Idle

State does notsetSI.

Table 20.1. SMB0STA Status Codes and States

Mode

Status

Code

SMBus State

Typical Action

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21.

ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0)

The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus.
SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves
on a single SPIbus. The slave-select (NSS) signal can be configured as an input to select SPI0 in slave mode, or to
disable Master Mode operation in a multi-master environment, avoiding contention on the SPIbus when more than
one master attempts simultaneous data transfers. NSS can also be configured as a chip-select output in master mode,
or disabled for 3-wire operation. Additional general purpose port I/O pins can be used to select multiple slave devices
in master mode.

Figure 21.1. SPI Block Diagram

SFR Bus

Data Path

Control

SFR Bus

Write

SPI0DAT

Receive Dat a Buffer

SPI0DAT

ShiftRegister

SPI CONTROL LOGIC

SPI0CKR

SCR7

SCR6

SCR5

SCR4

SCR3

SCR2

SCR1

SCR0

SPI0CFG

SPI0CN

Pin Interface

Control

Logic

C
R

S
S
B
A
R

PortI/O

Read

SPI0DAT

SPI IRQ

Tx Data

Rx Data

SCK

MOSI

MISO

NSS

TransmitData Buffer

Clock Divide

Logic

SYSCLK

CKPHA

CKPO

SEL

NSS

IBSY

NSSIN

RXB

WCOL

MOD

RXO

XBM

IEN

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21.1.

Signal Descriptions

The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below.

21.1.1. Master Out, Slave In (MOSI)

The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. This signal is an output when SPI0 is operating as a master and an
input when SPI0 is operating as a slave. Data is transferred most-significant bit first. When configured as a master,
MOSIis driven by the MSB of the shift register in both 3- and 4-wire mode.

21.1.2. Master In, Slave Out (MISO)

The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. This signal is an input when SPI0 is operating as a master and an
output when SPI0 is operating as a slave. Data is transferred most-significant bit first. The MISO pin is placed in a
high-impedance state when the SPImodule is disabled and when the SPIoperates in 4-wire mode as a slave that is
not selected. When acting as a slave in 3-wire mode, MISO is always driven by the MSB of the shift register.

21.1.3. Serial Clock (SCK)

The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to synchro-
nize the transfer of data between the master and slave on the MOSIand MISO lines. SPI0 generates this signal when
operating as a master. The SCK signal is ignored by a SPIslave when the slave is not selected (NSS = 1) in 4-wire
slave mode.

21.1.4. Slave Select (NSS)

The function of the slave-select (NSS) signal is dependent on the setting of the NSSMD1 and NSSMD0 bits in the
SPI0CN register. There are three possible modes that can be selected with these bits:

NSSMD[1:0] = 00: 3-Wire Master or 3-Wire Slave Mode: SPI0 operates in 3-wire mode, and NSS is

disabled. When operating as a slave device, SPI0 is always selected in 3-wire mode. Since no select signal is
present, SPI0 must be the only slave on the bus in 3-wire mode. This is intended for point-to-point commu-
nication between a master and one slave.
2.

NSSMD[1:0] = 01: 4-Wire Slave or Multi-Master Mode: SPI0 operates in 4-wire mode, and NSS is

enabled as an input. When operating as a slave, NSS selects the SPI0 device. When operating as a master, a
1-to-0 transition of the NSS signal disables the master function of SPI0 so that multiple master devices can
be used on the same SPIbus.
3.

NSSMD[1:0] = 1x: 4-Wire Master Mode: SPI0 operates in 4-wire mode, and NSS is enabled as an out-

put. The setting of NSSMD0 determines what logic level the NSS pin will output. This configuration should
only be used when operating SPI0 as a master device.

See Figure 21.2, Figure 21.3, and Figure 21.4 for typical connection diagrams of the various operational modes. Note
that the setting of NSSMD bits affects the pinout of the device. When in 3-wire master or 3-wire slave mode, the
NSS pin will not be mapped by the crossbar. In all other modes, the NSS signal will be mapped to a pin on the device.
See Section "

19. PORT INPUT/OUTPUT

" on page

215

for general purpose port I/O and crossbar information.

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21.2.

SPI0 Master Mode Operation

A SPImaster device initiates all data transfers on a SPIbus. SPI0 is placed in master mode by setting the Master
Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode
writes to the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift reg-
ister, and a data transfer begins. The SPI0 master immediately shifts out the data serially on the MOSI line while pro-
viding the serial clock on SCK. The SPIF (SPI0CN.7) flag is set to logic 1 at the end of the transfer. If interrupts are
enabled, an interrupt request is generated when the SPIF flag is set. While the SPI0 master transfers data to a slave on
the MOSIline, the addressed SPIslave device simultaneously transfers the contents of its shift register to the SPI
master on the MISO line in a full-duplex operation. Therefore, the SPIF flag serves as both a transmit-complete and
receive-data-ready flag. The data byte received from the slave is transferred MSB-first into the master's shift register.
When a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.

When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire single-
master mode, and 4-wire single-master mode. The default, multi-master mode is active when NSSMD1 (SPI0CN.3) =
0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and is used to disable the master SPI0
when another master is accessing the bus. When NSS is pulled low in this mode, MSTEN (SPI0CN.6) and SPIEN
(SPI0CN.0) are set to 0 to disable the SPI master device, and a Mode Fault is generated (MODF, SPI0CN.5 = 1).
Mode Fault will generate an interrupt if enabled. SPI0 must be manually re-enabled in software under these circum-
stances. In multi-master systems, devices will typically default to being slave devices while they are not acting as the
system master device. In multi-master mode, slave devices can be addressed individually (if needed) using general-
purpose I/O pins. Figure 21.2 shows a connection diagram between two master devices in multiple-master mode.

3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this mode,
NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices that must be
addressed in this mode should be selected using general-purpose I/O pins. Figure 21.3 shows a connection diagram
between a master device in 3-wire master mode and a slave device.

4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an output
pin, and can be used as a slave-select signal for a single SPIdevice. In this mode, the output value of NSS is con-
trolled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be addressed using general-pur-
pose I/O pins. Figure 21.4 shows a connection diagram for a master device in 4-wire master mode and two slave
devices.

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21.3.

SPI0 Slave Mode Operation

When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in
through the MOSIpin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in
the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic
1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave
device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writ-
ing to SPI0DAT. Writes to SPI0DAT are double-buffered, and are placed in the transmit buffer first. If the shift regis-
ter is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift
register already contains data, the SPIwill load the shift register with the transmit buffer's contents after the last SCK
edge of the next (or current) SPItransfer.

When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode,
is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the NSS signal is routed to
a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1.
The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks
before the first active edge of SCK for each byte transfer. Figure 21.4 shows a connection diagram between two slave
devices in 4-wire slave mode and a master device.

3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this
mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing
the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in
3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been
received. The bit counter can only be reset by disabling and re-enabling SPI0 with the SPIEN bit. Figure 21.3 shows
a connection diagram between a slave device in 3-wire slave mode and a master device.

21.4.

SPI0 Interrupt Sources

When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1:

Note that all of the following bits must be cleared by software.

The SPIInterrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can

occur in all SPI0 modes.
2.

The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when

the transmit buffer has not been emptied to the SPIshift register. When this occurs, the write to SPI0DAT
will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes.
3.

The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for

multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the MSTEN and SPIEN bits
in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
4.

The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a

transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte
is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte
which caused the overrun is lost.

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21.5.

Serial Clock Timing

Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configu-
ration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the
data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave
devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN
bit, SPI0CN.0) when changing the clock phase or polarity. The clock and data line relationships for master mode are
shown in Figure 21.5. For slave mode, the clock and data relationships are shown in Figure 21.6 and Figure 21.7.
Note that CKPHA must be set to `0' on both the master and slave SPIwhen communicating between two of the fol-
lowing devices: C8051F04x, C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x

The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 21.10 controls the master mode serial clock frequency.
This register is ignored when operating in slave mode. When the SPIis configured as a master, the maximum data
transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPIis con-
figured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock fre-
quency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously
with the slave's system clock. If the master issues SCK, NSS, and the serial input data asynchronously, the maximum
data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master
only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation),
the SPIslave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is
provided that the master issues SCK, NSS, and the serial input data synchronously with the slave's system clock.

SCK
(CKPOL=0, CKPHA=0)

SCK
(CKPOL=0, CKPHA=1)

SCK
(CKPOL=1, CKPHA=0)

SCK
(CKPOL=1, CKPHA=1)

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

MISO/MOSI

NSS (MustRemain High
in Multi-Master Mode)

Figure 21.5. Master Mode Data/Clock Timing

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21.6.

SPI Special Function Registers

SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg-
ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special
function registers related to the operation of the SPI0 Bus are described in the following figures.

Figure 21.8. SPI0CFG: SPI0 Configuration Register

Bit 7:

SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPItransfer is in progress (Master or slave Mode).

Bit 6:

MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.

Bit 5:

CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.

0: Data centered on first edge of SCK period.

1: Data centered on second edge of SCK period.

Bit 4:

CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.

Bit 3:

SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is
cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous
value at the NSS pin, but rather a de-glitched version of the pin input.

Bit 2:

NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register
is read. This input is not de-glitched.

Bit 1:

SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is
no new information available to read from the transmit buffer or write to the receive buffer. It returns
to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition
on SCK.
NOTE: SRMT = 1 when in Master Mode.

Bit 0:

RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new information.
If there is new information available in the receive buffer that has not been read, this bit will return to
logic 0.
NOTE: RXBMT = 1 when in Master Mode.

In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled

one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device. See Table 21.1
for timing parameters.

R/W

Reset Value

SPIBSY

MSTEN

CKPHA

CKPOL

SLVSEL

NSSIN

SRMT

RXBMT

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x9A
0

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Figure 21.9. SPI0CN: SPI0 Control Register

Bit 7:

SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this
bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared
by hardware. It must be cleared by software.

Bit 6:

WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0
data register was attempted while a data transfer was in progress. It must be cleared by software.

Bit 5:

MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is
detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by
hardware. It must be cleared by software.

Bit 4:

RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still
holds unread data from a previous transfer and the last bit of the current transfer is shifted into the
SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software.

Bits 3-2:

NSSMD1-NSSMD0: Slave Select Mode.
Selects between the following NSS operation modes:
(See

Section "21.2. SPI0 Master Mode Operation" on page 251

and

Section "21.3. SPI0 Slave

Mode Operation" on page 253

00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume
the value of NSSMD0.

Bit 1:

TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the
transmit buffer is transferred to the SPIshift register, this bit will be set to logic 1, indicating that it is
safe to write a new byte to the transmit buffer.

Bit 0:

SPI EN: SPI 0 Enable.
This bit enables/disables the SPI.
0: SPIdisabled.
1: SPIenabled.

R/W

Reset Value

SPIF

WCOL

MODF

RXOVRN

NSSMD1

NSSMD0

TXBMT

SPIEN

00000110

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0xF8
0

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Table 21.1. SPI Slave Timing Parameters

PARAMETER

DESCRIPTIONMIN

MAX

ITS

MASTER MODE TIMING

(See Figure 21.12 and Figure 21.13)

MCKH

SCK High Time

1*T

SYSCLK

MCKL

SCK Low Time

1*T

SYSCLK

MIS

MISO Valid to SCK Shift Edge

1*T

SYSCLK

+ 20

MIH

SCK Shift Edge to MISO Change

SLAVE MODE TIMIN G

(See Figure 21.14 and Figure 21.15)

NSS Falling to First SCK Edge

2*T

SYSCLK

Last SCK Edge to NSS Rising

2*T

SYSCLK

SEZ

NSS Falling to MISO Valid

4*T

SYSCLK

SDZ

NSS Rising to MISO High-Z

4*T

SYSCLK

CKH

SCK High Time

5*T

SYSCLK

CKL

SCK Low Time

5*T

SYSCLK

SIS

MOSIValid to SCK Sample Edge

2*T

SYSCLK

SIH

SCK Sample Edge to MOSIChange

2*T

SYSCLK

SOH

SCK Shift Edge to MISO Change

4*T

SYSCLK

SLH

Last SCK Edge to MISO Change (CKPHA = 1 ONLY)

6*T

SYSCLK

8*T

SYSCLK

is equal to one period of the device system clock (SYSCLK).

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22.

UART0

UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate
in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully sup-
ported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data
byte before software has finished reading the previous data byte. A Receive Overrun bit indicates when new received
data is latched into the receive buffer before the previously received byte has been read.

UART0 is accessed via its associated SFR's, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single
SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses the Receive register
and writing SCON0 accesses the Transmit register.

UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit Interrupt flag,
TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set
when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors
to the interrupt service routine; they must be cleared manually by software. This allows software to determine the
cause of the UART0 interrupt (transmit complete or receive complete).

Figure 22.1. UART0 Block Diagram

Tx Control

Tx Clock

Tx IRQ

Zero Detector

Send

Shift

SET

CLR

Stop Bit

Gen.

TB80

Start

Data

Write to

SBUF0

Crossbar

TX0

PortI/O

Serial Port

(UART0) Interrupt

Rx Control

Start

Rx Clock

Load

SBUF

0x1FF

Shift

Rx IRQ

UART0

Baud Rate Generation

Logic

SFR Bus

InputShiftRegister

(9 bits)

Frame Error

Detection

SBUF0

Read

SBUF0

SFR Bus

SADDR0

SADEN0

Match Detect

RB80

Load
SBUF0

Crossbar

RX0

SBUF0

Address

Match

SCON0

2
0

T
B
8
0

R
B

8
0

1
0

0
0

R
E
N

SSTA0

T
X
C

L
0

S
0
T
C
L
K
1

S
0
R
C
L
K
1

R
X
O
V

F
E
0

M
O
D

TI0

RI0

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22.1.

UART0 Operational Modes

UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration
bits in the SCON0 register. These four modes offer different baud rates and communication protocols. The four
modes are summarized in Table 22.1.

22.1.1. Mode 0: Synchronous Mode

Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX0 pin.
The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 22.3).

Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are transferred
LSB first (see the timing diagram in Figure 22.2), and the TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of
the eighth bit time. Data reception begins when the REN0 Receive Enable bit (SCON0.4) is set to logic 1 and the RI0
Receive Interrupt Flag (SCON0.0) is cleared. One cycle after the eighth bit is shifted in, the RI0 flag is set and recep-
tion stops until software clears the RI0 bit. An interrupt will occur if enabled when either TI0 or RI0 are set.

The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will typically
be required.

Table 22.1. UART0 Modes

Mode

Synchronization

Baud Clock

Data Bits

Start/Stop Bits

Synchronous

SYSCLK / 12

None

Asynchronous

Timer 1, 2, 3, or 4 Overflow

1 Start, 1 Stop

Asynchronous

SYSCLK / 32 or SYSCLK / 64

1 Start, 1 Stop

Asynchronous

Timer 1, 2, 3, or 4 Overflow

1 Start, 1 Stop

Figure 22.2. UART0 Mode 0 Timing Diagram

RX (data out)

MODE 0 TRANSMIT

MODE 0 RECEIVE

RX (data in)

TX (clk out)

Figure 22.3. UART0 Mode 0 Interconnect

Shift

Reg.

CLK

C8051Fxxx

DATA

8 Extra Outputs

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22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate

Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start
bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin.
On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).

Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt
Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if SM20
is logic 1, the stop bit must be logic 1.

I f these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the RI 0 flag is
set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt
will occur if enabled when either TI0 or RI0 are set.

The baud rate generated in Mode 1 is a function of timer overflow, shown in Equation 22.1 and Equation 22.2.
UART0 can use Timer 1 operating in 8-Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating in Auto-reload Mode to
generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a roll-
over from all ones - (0xFF for Timer 1, 0xFFFF for Timer 2) - to zero) a clock is sent to the baud rate logic.

Timers 2, 3, and 4 are selected as the baud rate source with bits in the SSTA0 register (see Figure 22.9). The transmit
baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive baud rate clock is selected using
the S0RCLK1 and S0RCLK0 bits.

The Mode 1 baud rate equations are shown below, where T1M is bit4 of register CKCON, TH1 is the 8-bit reload reg-
ister for Timer 1, and [RCAPnH , RCAPnL] is the 16-bit reload register for Timer 2, 3, or 4.

Figure 22.4. UART0 Mode 1 Timing Diagram

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

Equation 22.1. Mode 1 Baud Rate using Timer 1

BaudRate

SMOD0

-------------------

SYSCLK

T1M

)

(

)

256

TH1

(

)

--------------------------------------------------------

Equation 22.2. Mode 1 Baud Rate using Timer 2, 3, or 4

BaudRate

SYSCLK

65536

RCAPnH RCAPnL

[

]

(

)

---------------------------------------------------------------------------------------------

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22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate

Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data
bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and
hardware address recognition (see

Section 22.2

). On transmit, the ninth data bit is determined by the value in TB80

(SCON0.3). It can be assigned the value of the parity flag P in the PSW or used in multiprocessor communications.
On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored.

Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt
Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met:

SM20 is logic 0

SM20 is logic 1, the received 9th bit is logic 1, and the received address matches the UART0 address as
described in

Section 22.2

If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set.
An interrupt will occur if enabled when either TI0 or RI0 are set.

The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, according to the value of the SMOD0 bit in register
SSTA0.

Equation 22.3. Mode 2 Baud Rate

BaudRate

SMOD0

SYSCLK

----------------------

Figure 22.5. UART0 Modes 2 and 3 Timing Diagram

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

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22.2.

Multiprocessor Communications

Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors
by special use of the ninth data bit and the built-in UART0 address recognition hardware. When a master processor
wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs
from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. UART0 will recog-
nize as "valid" (i.e., capable of causing an interrupt) two types of addresses: (1) a masked address and (2) a broadcast
address at any given time. Both are described below.

22.2.1. Configuration of a Masked Address

The UART0 address is configured via two SFR's: SADDR0 (Serial Address) and SADEN0 (Serial Address Enable).
SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 correspond to bits in
SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0 correspond to "don't
care" bits in SADDR0.

Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will generate an
interrupt only if the ninth bit is logic 1 (RB80 = `1') and the received data byte matches the UART0 slave address.
Following the received address interrupt, the slave will clear its SM20 bit to enable interrupts on the reception of the
following data byte(s). Once the entire message is received, the addressed slave resets its SM20 bit to ignore all trans-
missions until it receives the next address byte. While SM20 is logic 1, UART0 ignores all bytes that do not match the
UART0 address and include a ninth bit that is logic 1.

22.2.2. Broadcast Addressing

Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast address is the logi-
cal OR of registers SADDR0 and SADEN0, and `0's of the result are treated as "don't cares". Typically a broadcast
address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming "don't care" bits as `1's. The master proces-
sor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is
temporarily reversed to enable half-duplex transmission between the original master and slave(s)..

Note in the above examples 4, 5, and 6, each slave would recognize as "valid" an address of 0xFF as a broadcast
address. Also note that examples 4, 5, and 6 uses the same SADDR0 and SADEN0 register values as shown in the
examples 1, 2, and 3 respectively (slaves #1, 2, and 3). Thus, a master could address each slave device individually
using a masked address, and also broadcast to all three slave devices. For example, if a Master were to send an
address "11110101", only slave #1 would recognize the address as valid. If a master were to then send an address of
"11111111", all three slave devices would recognize the address as a valid broadcast address.

Example 1, SLAVE #1

Example 2, SLAVE #2

Example 3, SLAVE #3

SADDR0

= 00110101

SADDR0

= 00110101

SADDR0

= 00110101

SADEN0

= 00001111

SADEN0

= 11110011

SADEN0

= 11000000

UART0 Address

= xxxx0101

UART0 Address

= 0011xx01

UART0 Address

= 00xxxxxx

Example 4, SLAVE #1

Example 5, SLAVE #2

Example 6, SLAVE #3

SADDR0

= 00110101

SADDR0

= 00110101

SADDR0

= 00110101

SADEN0

= 00001111

SADEN0

= 11110011

SADEN0

= 11000000

Broadcast Address = 00111111

Broadcast Address = 11110111

Broadcast Address = 11110101

Where all ZEROES in the Broadcast address are don't cares.

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Table 22.2. Oscillator Frequencies for Standard Baud Rates

System Clock Frequency

(MHz)

Divide Factor Timer 1 Reload

Value*

Timer 2, 3, or 4

Reload Value

Resulting Baud Rate (Hz)**

100.0

864

0xCA

0xFFCA

115200 (115741)

99.5328

864

0xCA

0xFFCA

115200

50.0

432

0xE5

0xFFE5

115200 (115741)

49.7664

432

0xE5

0xFFE5

115200

24.0

208

0xF3

0xFFF3

115200 (115384)

22.1184

192

0xF4

0xFFF4

115200

18.432

160

0xF6

0xFFF6

115200

11.0592

0xFA

0xFFFA

115200

3.6864

0xFE

0xFFFE

115200

1.8432

0xFF

0xFFFF

115200

100.0

3472

0x27

0xFF27

28800 (28802)

99.5328

3456

0x28

0xFF28

28800

50.0

1744

0x93

0xFF93

28800 (28670)

49.7664

1728

0x94

0xFF94

28800

24.0

832

0xCC

0xFFCC

28800 (28846)

22.1184

768

0xD0

0xFFD0

28800

18.432

640

0xD8

0xFFD8

28800

11.0592

348

0xE8

0xFFE8

28800

3.6864

128

0xF8

0xFFF8

28800

1.8432

0xFC

0xFFFC

28800

100.0

10416

0xFD75

9600 (9601)

99.5328

10368

0xFD78

9600

50.0

5216

0xFEBA

9600 (9586)

49.7664

5184

0xFEBC

9600

24.0

2496

0x64

0xFF64

9600 (9615)

22.1184

2304

0x70

0xFF70

9600

18.432

1920

0x88

0xFF88

9600

11.0592

1152

0xB8

0xFFB8

9600

3.6864

384

0xE8

0xFFE8

9600

1.8432

192

0xF4

0xFFF4

9600

* Assumes SMOD0=1 and T1M=1.
** Numbers in parenthesis show the actual baud rate.

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Figure 22.8. SCON0: UART0 Control Register

Bits7-6:

SM00-SM10: Serial Port Operation Mode:
Write:
When written, these bits select the Serial Port Operation Mode as follows:

Reading these bits returns the current UART0 mode as defined above.

Bit5:

SM20: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect
Mode 1: Checks for valid stop bit.

0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.

Mode 2 and 3: Multiprocessor Communications Enable.

0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received
address matches the UART0 address or the broadcast address.

Bit4:

REN0: Receive Enable.
This bit enables/disables the UART0 receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.

Bit3:

TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used
in Modes 0 and 1. Set or cleared by software as required.

Bit2:

RB80: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM20 is
logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0.

Bit1:

TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in Mode 0, or
at the beginning of the stop bit in other modes). When the UART0 interrupt is enabled, setting this bit
causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually
by software

Bit0:

RI0: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART0 (as selected by the SM20 bit).
When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 inter-
rupt service routine. This bit must be cleared manually by software.

R/W

Reset Value

SM00

SM10

SM20

REN0

TB80

RB80

TI0

RI0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x98
0

SM00

SM10

Mode

Mode 0: Synchronous Mode

Mode 1: 8-Bit UART, Variable Baud Rate

Mode 2: 9-Bit UART, Fixed Baud Rate

Mode 3: 9-Bit UART, Variable Baud Rate

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Figure 22.9. SSTA0: UART0 Status and Clock Selection Register

Bit7:

FE0: Frame Error Flag.

This flag indicates if an invalid (low) STOP bit is detected.
0: Frame Error has not been detected
1: Frame Error has been detected.

Bit6:

RXOV0: Receive Overrun Flag.

This flag indicates new data has been latched into the receive buffer before software has read the pre-
vious byte.
0: Receive overrun has not been detected.
1: Receive Overrun has been detected.

Bit5:

TXCOL0: Transmit Collision Flag.

This flag indicates user software has written to the SBUF0 register while a transmission is in
progress.
0: Transmission Collision has not been detected.
1: Transmission Collision has been detected.

Bit4:

SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations
described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.

Bits3-2:

UART0 Transmit Baud Rate Clock Selection Bits.

Bits1-0:

UART0 Receive Baud Rate Clock Selection Bits

Note: FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions.

R/W

Reset Value

FE0

RXOV0

TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x91
0

S0TCLK1

S0TCLK0

Serial Transmit Baud Rate Clock Source

Timer 1 generates UART0 TX Baud Rate

Timer 2 Overflow generates UART0 TX baud rate

Timer 3 Overflow generates UART0 TX baud rate

Timer 4 Overflow generates UART0 TX baud rate

S0RCLK1

S0RCLK0 Serial Receive Baud Rate Clock Source

Timer 1 generates UART0 RX Baud Rate

Timer 2 Overflow generates UART0 RX baud rate

Timer 3 Overflow generates UART0 RX baud rate

Timer 4 Overflow generates UART0 RX baud rate

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Figure 22.10. SBUF0: UART0 Data Buffer Register

Bits7-0:

SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB)
This is actually two registers; a transmit and a receive buffer register. When data is moved to SBUF0,
it goes to the transmit buffer and is held for serial transmission. Moving a byte to SBUF0 is what ini-
tiates the transmission. When data is moved from SBUF0, it comes from the receive buffer.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x99
0

Figure 22.11. SADDR0: UART0 Slave Address Register

Bits7-0:

SADDR0.[7:0]: UART0 Slave Address
The contents of this register are used to define the UART0 slave address. Register SADEN0 is a bit
mask to determine which bits of SADDR0 are checked against a received address: corresponding bits
set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0 are "don't cares".

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xA9
0

Figure 22.12. SADEN0: UART0 Slave Address Enable Register

Bits7-0:

SADEN0.[7:0]: UART0 Slave Address Enable
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0 slave
address.
0: Corresponding bit in SADDR0 is a "don't care".
1: Corresponding bit in SADDR0 is checked against a received address.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xB9
0

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23.

UART1

UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced
baud rate support allows a wide range of clock sources to generate standard baud rates (details in

Section

"23.1. Enhanced Baud Rate Generation" on page 276

). Received data buffering allows UART1 to start reception

of a second incoming data byte before software has finished reading the previous data byte.

UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1). The single
SBUF1 location provides access to both transmit and receive registers. Reading SBUF1 accesses the buffered
Receive register; writing SBUF1 accesses the Transmit register.

With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or
a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when
the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to
determine the cause of the UART1 interrupt (transmit complete or receive complete).

Figure 23.1. UART1 Block Diagram

UART1 Baud

Rate Generator

RI1

SCON1

Tx Control

Tx Clock

Send

SBUF1

(TX Shift)

Start

Data

Write to

SBUF1

Crossbar

TX1

Shift

Zero Detector

Tx IRQ

SET

CLR

Stop Bit

TB81

SFR Bus

Serial

Port

Interrupt

TI1

PortI/O

Rx Control

Start

Rx Clock

Load

SBUF1

Shift0x1FF

RB81

Rx IRQ

InputShiftRegister

(9 bits)

Load SBUF1

Read

SBUF1

SFR Bus

Crossbar

RX1

SBUF1

(RX Latch)

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C8051F124/5/6/7

23.1.

Enhanced Baud Rate Generation

The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX
clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-accessible. Both TX and
RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is
enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is
detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer
state.

Timer 1 should be configured for Mode 2, 8-bit auto-reload (see

Section "24.1.3. Mode 2: 8-bit Counter/Timer

with Auto-Reload" on page 287

). The Timer 1 reload value should be set so that overflows will occur at two times

the desired baud rate. Note that Timer 1 may be clocked by one of five sources: SYSCLK, SYSCLK / 4, SYSCLK /

12, SYSCLK / 48, or the external oscillator clock / 8. For any given Timer 1 clock source, the UART1 baud rate is

determined by Equation 23.1.

Where T1

CLK

is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value).

Timer 1 clock frequency is selected as described in

Section "24.1. Timer 0 and Timer 1" on page 285

. A quick ref-

erence for typical baud rates and system clock frequencies is given in Table 23.1 through Table 23.5. Note that the
internal oscillator or PLL may still generate the system clock when the external oscillator is driving Timer 1 (see

Sec-

tion "24.1. Timer 0 and Timer 1" on page 285

for more details).

Figure 23.2. UART1 Baud Rate Logic

RX Timer

Start

Detected

Overflow

TH1

TL1

TX Clock

RX Clock

Timer 1

UART1

Equation 23.1. UART1 Baud Rate

UARTBaudRate

CLK

256

T1H

(

)

-------------------------------

1
2

---

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23.2.

Operational Modes

UART1 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by
the S1MODE bit (SCON1.7). Typical UART connection options are shown below.

23.2.1. 8-Bit UART

8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data
are transmitted LSB first from the TX1 pin and received at the RX1 pin. On receive, the eight data bits are stored in
SBUF1 and the stop bit goes into RB81 (SCON1.2).

Data transmission begins when software writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt Flag
(SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any
time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte will
be loaded into the SBUF1 receive register if the following conditions are met: RI1 must be logic 0, and if MCE1 is
logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the
SBUF1 receive register and the following overrun data bits are lost.

I f these conditions are met, the eight bits of data is stored in SBUF1, the stop bit is stored in RB81 and the RI 1 flag is
set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set. An interrupt
will occur if enabled when either TI1 or RI1 is set.

Figure 23.3. UART Interconnect Diagram

RS-232

C8051Fxxx

RS-232

LEVEL

XLTR

C8051Fxxx

MCU

Figure 23.4. 8-Bit UART Timing Diagram

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

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C8051F124/5/6/7

23.2.2. 9-Bit UART

9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth
data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81 (SCON1.3), which
is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection,
or used in multiprocessor communications. On receive, the ninth data bit goes into RB81 (SCON1.2) and the stop bit
is ignored.

Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt
Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN1 Receive Enable bit (SCON1.4) is set to `1'. After the stop bit is received, the data byte will
be loaded into the SBUF1 receive register if the following conditions are met: (1) RI1 must be logic 0, and (2) if
MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the state of the ninth data bit is unimportant). If
these conditions are met, the eight bits of data are stored in SBUF1, the ninth bit is stored in RB81, and the RI1 flag is
set to `1'. If the above conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to
`1'. A UART1 interrupt will occur if enabled when either TI1 or RI1 is set to `1'.

Figure 23.5. 9-Bit UART Timing Diagram

START

BIT

MARK

STOP

BIT

BIT TIMES

BIT SAMPLING

SPACE

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23.3.

Multiprocessor Communications

9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave pro-
cessors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first
sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in
a data byte, the ninth bit is always set to logic 0.

Setting the MCE1 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the
UART will generate an interrupt only if the ninth bit is logic one (RB81 = 1) signifying an address byte has been
received. In the UART interrupt handler, software should compare the received address with the slave's own assigned
8-bit address. If the addresses match, the slave should clear its MCE1 bit to enable interrupts on the reception of the
following data byte(s). Slaves that weren't addressed leave their MCE1 bits set and do not generate interrupts on the
reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed
slave should reset its MCE1 bit to ignore all transmissions until it receives the next address byte.

Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves,
thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be con-
figured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily
reversed to enable half-duplex transmission between the original master and slave(s).

Figure 23.6. UART Multi-Processor Mode Interconnect Diagram

Master
Device

Slave

Device

Slave

Device

Slave

Device

+5V

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C8051F124/5/6/7

Figure 23.7. SCON1: Serial Port 1 Control Register

Bit7:

S1MODE: Serial Port 1 Operation Mode.
This bit selects the UART1 Operation Mode.
0: Mode 0: 8-bit UART with Variable Baud Rate
1: Mode 1: 9-bit UART with Variable Baud Rate

Bit6:

UNUSED. Read = 1b. Write = don't care.

Bit5:

MCE1: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
Mode 0: Checks for valid stop bit.

0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.

Mode 1: Multiprocessor Communications Enable.

0: Logic level of ninth bit is ignored.
1: RI 1 is set and an interrupt is generated only when the ninth bit is logic 1.

Bit4:

REN1: Receive Enable.
This bit enables/disables the UART receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.

Bit3:

TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not
used in 8-bit UART Mode. Set or cleared by software as required.

Bit2:

RB81: Ninth Receive Bit.
RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in
Mode 1.

Bit1:

TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8-bit UART
Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1 interrupt is
enabled, setting this bit causes the CPU to vector to the UART1 interrupt service routine. This bit
must be cleared manually by software

Bit0:

RI1: Receive Interrupt Flag.
Set to `1' by hardware when a byte of data has been received by UART1 (set at the STOP bit sam-
pling time). When the UART1 interrupt is enabled, setting this bit to `1' causes the CPU to vector to
the UART1 interrupt service routine. This bit must be cleared manually by software.

R/W

Reset Value

S1MODE

MCE1

REN1

TB81

RB81

TI1

RI1

01000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x98
1

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C8051F124/5/6/7

Table 23.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator

Frequency: 24.5 MHz

Target
Baud Rate
(bps)

Baud Rate
% Error

Oscillator

Divide
Factor

Timer Clock
Source

SCA1-SCA0

(pre-scale select)

T1M

Timer 1
Reload
Value (hex)

SYS

f
r
om

Int

e
r
n

a
l

230400

-0.32%

106

SYSCLK

0xCB

115200

-0.32%

212

SYSCLK

0x96

57600

0.15%

426

SYSCLK

0x2B

28800

-0.32%

848

SYSCLK / 4

0x96

14400

0.15%

1704

SYSCLK / 12

0xB9

9600

-0.32%

2544

SYSCLK / 12

0x96

2400

-0.32%

10176

SYSCLK / 48

0x96

1200

0.15%

20448

SYSCLK / 48

0x2B

X = Don't care

SCA1-SCA0 and T1M bit definitions can be found in

Section 24.1

Table 23.2. Timer Settings for Standard Baud Rates Using an External Oscillator

Frequency: 25.0 MHz

Target
Baud Rate
(bps)

Baud Rate
% Error

Oscillator

Divide
Factor

Timer Clock
Source

SCA1-SCA0

(pre-scale select)

T1M

Timer 1
Reload
Value (hex)

SCL

f
r
om

Extern

s
c.

230400

-0.47%

108

SYSCLK

0xCA

115200

0.45%

218

SYSCLK

0x93

57600

-0.01%

434

SYSCLK

0x27

28800

0.45%

872

SYSCLK / 4

0x93

14400

-0.01%

1736

SYSCLK / 4

0x27

9600

0.15%

2608

EXTCLK / 8

0x5D

2400

0.45%

10464

SYSCLK / 48

0x93

1200

-0.01%

20832

SYSCLK / 48

0x27

f
r
om

Int

nal

sc.

57600

-0.47%

432

EXTCLK / 8

0xE5

28800

-0.47%

864

EXTCLK / 8

0xCA

14400

0.45%

1744

EXTCLK / 8

0x93

9600

0.15%

2608

EXTCLK / 8

0x5D

X = Don't care

SCA1-SCA0 and T1M bit definitions can be found in

Section 24.1

DS008-1.1-JUN03

Page 283

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Table 23.3. Timer Settings for Standard Baud Rates Using an External Oscillator

Frequency: 22.1184 MHz

Target
Baud Rate
(bps)

Baud Rate
% Error

Oscillator

Divide
Factor

Timer Clock
Source

SCA1-SCA0

(pre-scale select)

T1M

Timer 1
Reload
Value (hex)

SYS

f
r
om

Extern

s
c.

230400

0.00%

SYSCLK

0xD0

115200

0.00%

192

SYSCLK

0xA0

57600

0.00%

384

SYSCLK

0x40

28800

0.00%

768

SYSCLK / 12

0xE0

14400

0.00%

1536

SYSCLK / 12

0xC0

9600

0.00%

2304

SYSCLK / 12

0xA0

2400

0.00%

9216

SYSCLK / 48

0xA0

1200

0.00%

18432

SYSCLK / 48

0x40

SYSC

f
r
o

Int

ern

a
l

s
c
.

230400

0.00%

EXTCLK / 8

0xFA

115200

0.00%

192

EXTCLK / 8

0xF4

57600

0.00%

384

EXTCLK / 8

0xE8

28800

0.00%

768

EXTCLK / 8

0xD0

14400

0.00%

1536

EXTCLK / 8

0xA0

9600

0.00%

2304

EXTCLK / 8

0x70

X = Don't care

SCA1-SCA0 and T1M bit definitions can be found in

Section 24.1

Table 23.4. Timer Settings for Standard Baud Rates Using the PLL

Frequency: 50.0 MHz

Target
Baud Rate
(bps)

Baud Rate
% Error

Oscillator

Divide
Factor

Timer Clock
Source

SCA1-SCA0

(pre-scale select)

T1M

Timer 1
Reload
Value (hex)

230400

0.45%

218

SYSCLK

0x93

115200

-0.01%

434

SYSCLK

0x27

57600

0.45%

872

SYSCLK / 4

0x93

28800

-0.01%

1736

SYSCLK / 4

0x27

14400

0.22%

3480

SYSCLK / 12

0x6F

9600

-0.01%

5208

SYSCLK / 12

0x27

2400

-0.01%

20832

SYSCLK / 48

0x27

X = Don't care

SCA1-SCA0 and T1M bit definitions can be found in

Section 24.1

DS008-1.1-JUN03

Page 285

Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

24.

TIMERS

Each MCU includes 5 counter/timers: Timer 0 and Timer 1 are 16-bit counter/timers compatible with those found in
the standard 8051. Timer 2, Timer 3, and Timer 4 are 16-bit auto-reload and capture counter/timers for use with the
ADC, DAC's, square-wave generation, or for general-purpose use. These timers can be used to measure time inter-
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have
four primary modes of operation. Timer 3 offers 16-bit auto-reload and capture. Timers 2 and 4 are identical, and
offer not only 16-bit auto-reload and capture, but have the ability to produce a 50% duty-cycle square-wave (toggle
output) at an external port pin.

Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M-T0M) and
the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock by which Timer 0 and/or Timer 1
may be clocked (See Figure 24.6 for pre-scaled clock selection).

Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2, 3, or 4 may be
clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8.

Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer register is
incremented on each high-to-low transition at the selected input pin. Events with a frequency of up to one-fourth the
system clock's frequency can be counted. The input signal need not be periodic, but it should be held at a given logic
level for at least two full system clock cycles to ensure the level is properly sampled.

24.1.

Timer 0 and Timer 1

Each timer is implemented as 16-bit register accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte
(TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate
their status. Timer 0 interrupts can be enabled by setting the ET0 bit in the IE register (

Section "12.7.5. Interrupt

Register Descriptions" on page 149

); Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register

(

Section 12.7.5

). Both counter/timers operate in one of four primary modes selected by setting the Mode Select bits

T1M1-T0M0 in the Counter/Timer Mode register (TMOD). Each timer can be configured independently.

24.1.1. Mode 0: 13-bit Counter/Timer

Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and oper-
ation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as
described for Timer 0.

The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when read-
ing. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag
TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled.

The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions
at the selected Timer 0 input pin (T0) increment the timer register (Refer to

Section "19.1. Ports 0 through 3 and

the Priority Crossbar Decoder" on page 217

for information on selecting and configuring external I/O pins). Clear-

ing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is clocked by the system

Timer 0 and Timer 1 Modes:

Timer 2, 3 and 4 Modes:

13-bit counter/timer

16-bit counter/timer with auto-reload

16-bit counter/timer

16-bit counter/timer with capture

8-bit counter/timer with auto-reload

Toggle Output (Timer 2 and 4 only)

Two 8-bit counter/timers (Timer 0 only)

Page 286

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C8051F120/1/2/3
C8051F124/5/6/7

clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see
Figure 24.6).

Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is
logic-level 1. Setting GATE0 to `1' allows the timer to be controlled by the external input signal /INT0 (see

Section

"12.7.5. Interrupt Register Descriptions" on page 149

), facilitating pulse width measurements.

Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before
the timer is enabled.

TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1
is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is
used with Timer 1.

24.1.2. Mode 1: 16-bit Counter/Timer

Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are
enabled and configured in Mode 1 in the same manner as for Mode 0.

TR0

GATE0

/INT0

Counter/Timer

Disabled

Enabled

Disabled

Enabled

X = Don't Care

Figure 24.1. T0 Mode 0 Block Diagram

TCLK

TL0

(5 bits)

TH0

(8 bits)

TF0

TR0

TR1

TF1

IE1
IT1
IE0
IT0

Interrupt

TR0

SYSCLK

Pre-scaled Clock

CKCON

S
C
A

T
1

T
0

TMOD

T
1

G
A

T
E
1

G
A

T
E
0

T
0

GATE0

/INT0

Crossbar

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload

Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value.
TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to 0x00, the
timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are
enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initial-
ized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates
identically to Timer 0.

Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit
(TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is low.

Figure 24.2. T0 Mode 2 Block Diagram

TCLK

TMOD

T
1

A
T
E

T
0

TF0

TR0

TR1

TF1

IE1
IT1
IE0
IT0

Interrupt

TL0

(8 bits)

Reload

TH0

(8 bits)

SYSCLK

Pre-scaled Clock

CKCON

S
C
A

T
1

T
0

TR0

GATE0

/INT0

Crossbar

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)

In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0
is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. TL0 can use
either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function
sourced by the system clock or prescaled clock. TH0 is enabled using the Timer 1 run control bit TR1. TH0 sets the
Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.

Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but
cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow
can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is
operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in
Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.

Figure 24.3. T0 Mode 3 Block Diagram

TL0

(8 bits)

TMOD

TF0

TR0

TR1

TF1

IE1
IT1
IE0
IT0

Interrupt

SYSCLK

Pre-scaled Clock

TR1

TH0

(8 bits)

CKCON

S
C
A

T
1

T
0

T
1

A
T
E

T
0

TR0

GATE0

/INT0

Crossbar

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 24.4. TCON: Timer Control Register

Bit7:

TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically
cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.

Bit6:

TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.

Bit5:

TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically
cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.

Bit4:

TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.

Bit3:

IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared
by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service
routine if IT1 = 1. This flag is the inverse of the /INT1 signal.

Bit2:

IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be falling-edge sensitive or active-low.
0: /INT1 is level triggered, active-low.
1: /INT1 is edge triggered, falling-edge.

Bit1:

IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be cleared
by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service
routine if IT0 = 1. This flag is the inverse of the /INT0 signal.

Bit0:

IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be falling-edge sensitive or active-low.
0: /INT0 is level triggered, active logic-low.
1: /INT0 is edge triggered, falling-edge.

R/W

Reset Value

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address:

SFR Page:

0x88
0

Page 290

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 24.5. TMOD: Timer Mode Register

Bit7:

GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /I NT1 = logic 1.

Bit6:

C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin (T1).

Bits5-4:

T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.

Bit3:

GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /I NT0 = logic 1.

Bit2:

C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin (T0).

Bits1-0:

T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.

R/W

Reset Value

GATE1

C/T1

T1M1

T1M0

GATE0

C/T0

T0M1

T0M0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x89
0

T1M1

T1M0

Mode

Mode 0: 13-bit counter/timer

Mode 1: 16-bit counter/timer

Mode 2: 8-bit counter/timer with auto-reload

Mode 3: Timer 1 inactive

T0M1

T0M0

Mode

Mode 0: 13-bit counter/timer

Mode 1: 16-bit counter/timer

Mode 2: 8-bit counter/timer with auto-reload

Mode 3: Two 8-bit counter/timers

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 24.6. CKCON: Clock Control Register

Bits7-5:

UNUSED. Read = 000b, Write = don't care.

Bit4:

T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.

Bit3:

T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.

Bit2:

UNUSED. Read = 0b, Write = don't care.

Bits1-0:

SCA1-SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use
prescaled clock inputs.

Note: External clock divided by 8 is synchronized with the system clock.

R/W

Reset Value

T1M

T0M

SCA1

SCA0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8E
0

SCA1

SCA0

Prescaled Clock

System clock divided by 12

System clock divided by 4

System clock divided by 48

External clock divided by 8

Page 292

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

Figure 24.7. TL0: Timer 0 Low Byte

Bits 7-0:

TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8A
0

Figure 24.8. TL1: Timer 1 Low Byte

Bits 7-0:

TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8B
0

Figure 24.9. TH0: Timer 0 High Byte

Bits 7-0:

TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8C
0

Figure 24.10. TH1: Timer 1 High Byte

Bits 7-0:

TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0x8D
0

DS008-1.1-JUN03

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Preliminary

C8051F120/1/2/3
C8051F124/5/6/7

24.2.

Timer 2, Timer 3, and Timer 4

Timers 2, 3, and 4 are 16-bit counter/timers, each formed by two 8-bit SFR's: TMRnL (low byte) and TMRnH (high
byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. Timers 2 and 4 feature auto-reload, capture, and toggle
output modes with the ability to count up or down. Timer 3 features auto-reload and capture modes, with the ability to
count up or down. Capture Mode and Auto-reload mode are selected using bits in the Timer 2, 3, and 4 Control regis-
ters (TMRnCN). Toggle output mode is selected using the Timer 2 or 4 Configuration registers (TMRnCF). These
timers may also be used to generate a square-wave at an external pin. As with Timers 0 and 1, Timers 2, 3, and 4 can
use either the system clock (divided by one, two, or twelve), external clock (divided by eight) or transitions on an
external input pin as its clock source. The Counter/Timer Select bit C/Tn bit (TMRnCN.1) configures the peripheral
as a counter or timer. Clearing C/Tn configures the Timer to be in a timer mode (i.e., the system clock or transitions
on an external pin as the input for the timer). When C/Tn is set to 1, the timer is configured as a counter (i.e., high-to-
low transitions at the Tn input pin increment (or decrement) the counter/timer register. Timer 3 and Timer 2 share the
T2 input pin. Refer to

Section "19.1. Ports 0 through 3 and the Priority Crossbar Decoder" on page 217

for

information on selecting and configuring external I/O pins for digital peripherals, such as the Tn pin. Timer 2 and 3
can be used to start an ADC Data Conversion and Timers 2, 3, and 4 can schedule DAC outputs. Only Timer 1 can be
used to generate baud rates for UART 1, and Timers 1, 2, 3, or 4 may be used to generate baud rates for UART 0.

Timer 2, 3, and 4 can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock divided
by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Counter/Timer with Capture
mode. Clearing the C/Tn bit (TnCON.1) selects the system clock/external clock as the input for the timer. The Timer
Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the system clock undivided, system clock
divided by two, system clock divided by 12, or an external clock provided at the XTAL1/XTAL2 pins divided by 8
(see Figure 24.14). When C/Tn is set to logic 1, a high-to-low transition at the Tn input pin increments the counter/
timer register (i.e., configured as a counter).

24.2.1. Configuring Timer 2, 3, and 4 to Count Down

Timers 2, 3, and 4 have the ability to count down. When the timer's Decrement Enable Bit (DCEN) in the Timer Con-
figuration Register (See Figure 24.14) is set to `1', the timer can then count up or down. When DCEN = 1, the direc-
tion of the timer's count is controlled by the TnEX pin's logic level (Timer 3 shares the T2EX pin with Timer 2).
When TnEX = 1, the counter/timer will count up; when TnEX = 0, the counter/timer will count down. To use this fea-
ture, TnEX must be enabled in the digital crossbar and configured as a digital input.

Note: When DCEN = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not available.
TnEX will only control the direction of the timer when DCEN= 1.

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C8051F120/1/2/3
C8051F124/5/6/7

24.2.2. Capture Mode

In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the Timer Exter-
nal Enable bit (found in the TMRnCN register) is set to `1', a high-to-low transition on the TnEX input pin (Timer 3
shares the T2EX pin with Timer 2) causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the
capture registers (RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag
(TMRnCN.6) will be set to `1' and an interrupt will occur if the interrupt is enabled. See

Section "12.7. Interrupt

Handler" on page 146

for further information concerning the configuration of interrupt sources.

As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow Flag
(TMRnCN.7) is set to `1' and an interrupt will occur if the interrupt is enabled. The timer can be configured to count
down by setting the Decrement Enable Bit (TMRnCF.0) to `1'. This will cause the timer to decrement with every
timer clock/count event and underflow when the timer transitions from 0x0000 to 0xFFFF. Just as in overflows, the
Overflow/Underflow Flag (TFn) will be set to `1', and an interrupt will occur if enabled.

Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn (TMRnCN.0) and the
Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4 respective External Enable
EXENn (TnCON.3) must also be set to logic 1 to enable captures. If EXENn is cleared, transitions on TnEX will be
ignored.

TMRnL

TMRnH

TRn

TCLK

Interrupt

EXFn

EXENn

TRn

C/Tn

CP/RLn

TFn

SYSCLK

TMRnCF

D
C
E
N

T
n

O
G

T
n

Toggle Logic

(PortPin)

EXENn

Crossbar

TnEX

RCAPnL

RCAPnH

0xFF

External Clock

Crossbar

OVF

Capture

Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram

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C8051F120/1/2/3
C8051F124/5/6/7

24.2.3. Auto-Reload Mode

In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur
upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/underflow flag (TFn)
and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/Capture Registers
(RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. When the Timer External Enable Bit
(EXENn) bit is set to `1' and the Decrement Enable Bit (DCEN) is `0', a falling edge (`1'-to-`0' transition) on the
TnEX pin will cause a timer reload. Note that timer overflows will also cause auto-reloads. When DCEN is set to `1',
the state of the TnEX pin controls whether the counter/timer counts up (increments) or down (decrements), and will
not cause an auto-reload or interrupt event (Timer 3 shares the T2EX pin with Timer 2). See

Section 24.2.1

for infor-

mation concerning configuration of a timer to count down.

When counting down, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled)
when the value in the TMRnH and TMRnL registers matches the 16-bit value in the Reload/Capture Registers
(RCAPnH and RCAPnL). This is considered an underflow event, and will cause the timer to load the value 0xFFFF.
The timer is automatically restarted when an underflow occurs.

Counter/Timer with Auto-Reload mode is selected by clearing the CP/RLn bit. Setting TRn to logic 1 enables and
starts the timer.

In Auto-Reload Mode, the External Flag (EXFn) toggles upon every overflow or underflow and does not cause an
interrupt. The EXFn flag can be used as the most significant bit (MSB) of a 17-bit counter.

24.2.4. Toggle Output Mode (Timer 2 and Timer 4 Only)

Timers 2 and 4 have the capability to toggle the state of their respective output port pins (T2 or T4) to produce a 50%
duty cycle waveform output. The port pin state will change upon the overflow or underflow of the respective timer
(depending on whether the timer is counting up or down). The toggle frequency is determined by the clock source of

TMRnL

TMRnH

TRn

TCLK

Reload

Interrupt

EXENn

Crossbar

TnEX

EXFn

EXENn

TRn

C/Tn

CP/RLn

TFn

SYSCLK

TMRnCF

D
C
E
N

T
n

O
G

T
n

Toggle Logic

(PortPin)

RCAPnL

RCAPnH

0xFF

OVF

External Clock

Crossbar

SMBus

(Timer 4 Only)

Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram

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C8051F124/5/6/7

the timer and the values loaded into RCAPnH and RCAPnL. When counting DOWN, the auto-reload value for the
timer is 0xFFFF, and underflow will occur when the value in the timer matches the value stored in
RCAPnH:RCAPnL. When counting UP, the auto-reload value for the timer is RCAPnH:RCAPnL, and overflow will
occur when the value in the timer transitions from 0xFFFF to the reload value.

To output a square wave, the timer is placed in reload mode (the Capture/Reload Select Bit in TMRnCN and the
Timer/Counter Select Bit in TMRnCN are cleared to `0'). The timer output is enabled by setting the Timer Output
Enable Bit in TMRnCF to `1'. The timer should be configured via the timer clock source and reload/underflow values
such that the timer overflow/underflows at 1/2 the desired output frequency. The port pin assigned by the crossbar as
the timer's output pin should be configured as a digital output (see

Section "19. PORT INPUT/OUTPUT" on

page 215

). Setting the timer's Run Bit (TRn) to `1' will start the toggle of the pin. A Read/Write of the Timer's Tog-

gle Output State Bit (TMRnCF.2) is used to read the state of the toggle output, or to force a value of the output. This
is useful when it is desired to start the toggle of a pin in a known state, or to force the pin into a desired state when the
toggle mode is halted.

TCLK

65536

RCAPn

(

)

------------------------------------------------------

Equation 24.1. Square Wave Frequency (Timer 2 and Timer 4 Only)

If timer is configured to
count up:

If timer is configured to
count down:

TCLK

RCAPn

(

)

------------------------------------------

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Bit7:

TFn: Timer 2, 3, and 4 Overflow/Underflow Flag.
Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from the value
placed in RCAPnH:RCAPnL to 0xFFFF (in Auto-reload Mode), or underflows from 0x0000 to
0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit causes the CPU to
vector to the Timer interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.

Bit6:

EXFn: Timer 2, 3, or 4 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the TnEX
input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit causes the CPU
to vector to the Timer Interrupt service routine. This bit is not automatically cleared by hardware and
must be cleared by software.

Bit5-4:

Reserved.

Bit3:

EXENn: Timer 2, 3, and 4 External Enable.
Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direction of the
timer/counter (up or down count). If DECEN = 1, TnEX will determine if the timer counts up or
down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as a digital input.
0: Transitions on the TnEX pin are ignored.
1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count (up or
down) as follows:
Capture Mode: `1'-to-'0' Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer value.
Auto-Reload Mode:

DCEN = 0: `1'-to-'0' transition causes reload of timer and sets the EXFn Flag.
DCEN = 1: TnEX logic level controls direction of timer (up or down).

Bit2:

TRn: Timer 2, 3, and 4 Run Control.
This bit enables/disables the respective Timer.
0: Timer disabled.
1: Timer enabled and running/counting.

Bit1:

C/Tn: Counter/Timer Select.
0: Timer Function: Timer incremented by clock defined by TnM1:TnM0 (TMRnCF.4:TMRnCF.3).
1: Counter Function: Timer incremented by high-to-low transitions on external input pin.

Bit0:

CP/RLn: Capture/Reload Select.
This bit selects whether the Timer functions in capture or auto-reload mode.
0: Timer is in Auto-Reload Mode.
1: Timer is in Capture Mode.

Note: Timer 3 and Timer 2 share the T2 and T2EX pins.

R/W

Reset Value

TFn

EXFn

EXENn

TRn

C/Tn

CP/RLn

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bit

Addressable

SFR Address: TMR2CN:0xC8;TMR3CN:0xC8;TMR4CN:0xC8

SFR Page: TMR2CN: page 0;TMR3CN: page 1;TMR4CN: page 2

Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers

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C8051F124/5/6/7

Bit7-5:

Reserved.

Bit4-3:

TnM1 and TnM0: Timer Clock Mode Select Bits.
Bits used to select the Timer clock source. The sources can be the System Clock (SYSCLK),
SYSCLK divided by 2 or 12, or the external clock divided by 8. Clock source is selected as follows:
00: SYSCLK/12
01: SYSCLK
10: EXTERNAL CLOCK/8 (Synchronized to the System Clock)
11: SYSCLK/2

Bit2:

TOGn: Toggle output state bit.
When timer is used to toggle a port pin, this bit can be used to read the state of the output, or can be
written to in order to force the state of the output (Timer 2 and Timer 4 Only).

Bit1:

TnOE: Timer output enable bit.
This bit enables the timer to output a 50% duty cycle output to the timer's assigned external port pin.
NOTE: A timer is configured for Square Wave Output as follows:
CP/RLn = 0
C/Tn

= 1

TnOE= 1
Load RCAPnH:RCAPnL (See "Square Wave Frequency (Timer 2 and Timer 4 Only)" on page 296.)
Configure Port Pin to output squarewave (See

Section "19. PORT INPUT/OUTPUT" on page 215

)

0: Output of toggle mode not available at Timers's assigned port pin.
1: Output of toggle mode available at Timers's assigned port pin.

Bit0:

DCEN: Decrement Enable Bit.
This bit enables the timer to count up or down as determined by the state of TnEX.
0: Timer will count up, regardless of the state of TnEX.
1: Timer will count up or down depending on the state of TnEX as follows:

if TnEX = 0, the timer counts DOWN.
if TnEX = 1, the timer counts UP.

Note: Timer 3 and Timer 2 share the T2 and T2EX pins.

R/W

Reset Value

TnM1

TnM0

TOGn

TnOE

DCEN

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9

SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: Page 2

Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers

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Bits 7-0:

RCAP2, 3, and 4L: Timer 2, 3, and 4 Capture Register Low Byte.
The RCAP2, 3, and 4L register captures the low byte of Timer 2, 3, and 4 when Timer 2, 3, and 4 is
configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the
low byte of the reload value.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: RCAP2L: 0xCA; RCAP3L: 0xCA; RCAP4L: 0xCA

SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2

Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte

Figure 24.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte

Bits 7-0:

RCAP2, 3, and 4H: Timer 2, 3, and 4 Capture Register High Byte.
The RCAP2, 3, and 4H register captures the highballed of Timer 2, 3, and 4 when Timer 2, 3, and 4 is
configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the
high byte of the reload value.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: RCAP2H: 0xCB; RCAP3H: 0xCB; RCAP4H: 0xCB

SFR Page: RCAP2H: page 0; RCAP3H: page 1; RCAP4H: page 2

Figure 24.17. TMRnL: Timer 2, 3, and 4 Low Byte

Bits 7-0:

TL2, 3, and 4: Timer 2, 3, and 4 Low Byte.
The TL2, 3, and 4 register contains the low byte of the 16-bit Timer 2, 3, and 4

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: TMR2L: 0xCC; TMR3L: 0xCC; TMR4L: 0xCC

SFR Page: TMR2L: page 0; TMR3L: page 1; TMR4L: page 2

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25.

PROGRAMMABLE COUNTER ARRAY

The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU interven-
tion than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/
compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the
Crossbar to Port I/O when enabled (See

Section "19.1. Ports 0 through 3 and the Priority Crossbar Decoder" on

page 217

). The counter/timer is driven by a programmable timebase that can select between six inputs as its source:

system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source
divided by 8, Timer 0 overflow, or an external clock signal on the ECIline. Each capture/compare module may be
configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Out-
put, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each is described in

Section 25.2

). The PCA is configured and

controlled through the system controller's Special Function Registers. The basic PCA block diagram is shown in
Figure 25.1.

Figure 25.1. PCA Block Diagram

Capture/Compare

Module 1

Capture/Compare

Module 0

Capture/Compare

Module 2

Capture/Compare

Module 3

EX1

Crossbar

EX2

EX3

EX0

PortI/O

16-BitCounter/Timer

PCA

CLOCK

MUX

SYSCLK/12

SYSCLK/4

Timer 0 Overflow

ECI

SYSCLK

External Clock/8

Capture/Compare

Module 4

EX4

Capture/Compare

Module 5

EX5

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C8051F120/1/2/3
C8051F124/5/6/7

25.1.

PCA Counter/Timer

The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a "snapshot" register; the following PCA0H read accesses this "snapshot" register. Reading the PCA0L Register
first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb
the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 25.1.

When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be glo-
bally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7)
and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue
normal operation while the CPU is in Idle mode.

Note: External clock divided by 8 is synchronized with the system clock.

Table 25.1. PCA Timebase Input Options

CPS2

CPS1

CPS0

Timebase

System clock divided by 12

System clock divided by 4

Timer 0 overflow

High-to-low transitions on ECI(max rate = system clock divided by 4)

System clock

External oscillator source divided by 8

Figure 25.2. PCA Counter/Timer Block Diagram

PCA0MD

T
E

E
C
F

C
P
S

C
K

C
P
S

IDLE

PCA0H

PCA0L

Snapshot

To SFR Bus

Overflow

To PCA Interrupt System

PCA0L

read

To PCA Modules

SYSCLK/12

SYSCLK/4

Timer 0 Overflow

ECI

000

001

010

011

100

101

SYSCLK

External Clock/8

PCA0CN

C
R

C
C

F
0

C
C

F
2

C
C

F
1

C
C

F
5

C
C

F
4

C
C

F
3

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C8051F124/5/6/7

25.2.

Capture/Compare Modules

Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture,
Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modu-
lator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These
registers are used to exchange data with a module and configure the module's mode of operation.

Table 25.2 summarizes the bit settings in the PCA0CPMn registers used to select the PCA0 capture/compare mod-
ule's operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's CCFn interrupt. Note:
PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are glo-
bally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to logic 1. See Figure 25.3 for details on the
PCA interrupt configuration.

Table 25.2. PCA0CPM Register Settings for PCA Capture/Compare Modules

PWM16

ECOM

CAPP CAPNMAT

TOG

PWM

ECCF Operation Mode

Capture triggered by positive edge on

CEXn

Capture triggered by negative edge on

CEXn

Capture triggered by transition on

CEXn

Software Timer

High Speed Output

Frequency Output

8-Bit Pulse Width Modulator

16-Bit Pulse Width Modulator

X = Don't Care

Figure 25.3. PCA Interrupt Block Diagram

PCA0CN

C
R

C
C
F

C
C

F
5

C
C

F
4

C
C

F
3

PCA0MD

E
C
F

C
P
S

PCA Module 0

(CCF0)

PCA Module 1

(CCF1)

ECCF1

ECCF0

PCA Module 2

(CCF2)

ECCF2

PCA Module 3

(CCF3)

ECCF3

ECCF4

PCA Counter/

Timer Overflow

Interrupt
Priority
Decoder

EPCA0

(EIE.3)

PCA0CPMn

(for n = 0 t o 5)

W
M

1
6
n

E
C
O
M

E
C
C
F
n

O
G

C
A
P
P

C
A
P
N

M
A

T
n

PCA Module 4

(CCF4)

PCA Module 5

(CCF5)

(IE.7)

ECCF5

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C8051F120/1/2/3
C8051F124/5/6/7

25.2.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/timer and
load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn
and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-
high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge).
When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is
generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vec-
tors to the interrupt service routine, and must be cleared by software.

Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid.

Figure 25.4. PCA Capture Mode Diagram

PCA0L

PCA0CPLn

PCA
Timebase

CEXn

Crossbar

PortI/O

PCA0H

Capture

PCA0CPHn

(
to

CCF

)

PCA Interrupt

PCA0CPMn

W
M

1
6
n

E
C

O
M

E
C
C
F

O
G

W
M

C
A
P
P

C
A
P
N

A
T

PCA0CN

C
R

C
C

F
0

C
C

F
2

C
C

F
1

C
C

F
5

C
C

F
4

C
C

F
3

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25.2.4. Frequency Output Mode

Frequency Output Mode produces a programmable-frequency square wave on the module's associated CEXn pin.
The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The
frequency of the square wave is then defined by Equation 25.1.

Where F

PCA

is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD. The

lower byte of the capture/compare module is compared to the PCA0 counter low byte; on a match, CEXn is toggled
and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled
by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.

Equation 25.1. Square Wave Frequency Output

sqr

PCA

PCA0CPHn

-----------------------------------------

Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.

8-bit

Comparator

PCA0L

Enable

PCA Timebase

0 0 0

match

PCA0CPMn

1
6
n

E
C

O
M

E
C
C
F

O
G

C
A
P
P

C
A
P
N

T
n

PCA0CPHn

8-bitAdder

PCA0CPLn

Adder

Enable

CEXn

Crossbar

PortI/O

Toggle

TOGn

Figure 25.7. PCA Frequency Output Mode

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C8051F124/5/6/7

25.2.5. 8-Bit Pulse Width Modulator Mode

Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn
pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the
PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low
byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be
high. When the count value in PCA0L overflows, the CEXn output will be low (see Figure 25.8). Also, when the
counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value
stored in the counter/timer's high byte (PCA0H) without software intervention. Setting the ECOMn and PWMn bits
in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given
by Equation 25.2.

DutyCycle

256

PCA0CPHn

(

)

256

---------------------------------------------------

Equation 25.2. 8-Bit PWM Duty Cycle

8-bit

Comparator

PCA0L

PCA0CPLn

PCA0CPHn

CEXn

Crossbar

PortI/O

Enable

Overflow

PCA Timebase

0 0 0 0

SET

CLR

match

PCA0CPMn

1
6
n

E
C

O
M

E
C
C
F

O
G

C
A
P
P

C
A
P
N

A
T

Figure 25.8. PCA 8-Bit PWM Mode Diagram

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25.2.6. 16-Bit Pulse Width Modulator Mode

Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module
defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module
contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is
enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle,
CCFn should also be set to logic 1 to enable match interrupts. The duty cycle for 16-Bit PWM Mode is given by

Equation 25.3. 16-Bit PWM Duty Cycle

DutyCycle

65536

PCA0CPn

(

)

65536

-----------------------------------------------------

Figure 25.9. PCA 16-Bit PWM Mode

PCA0CPLn

PCA0CPHn

Enable

PCA Timebase

0 0 0 0

PCA0CPMn

1
6
n

E
C

O
M

E
C
C
F

O
G

C
A
P
P

C
A
P
N

A
T

16-bitComparator

CEXn

Crossbar

PortI/O

Overflow

SET

CLR

match

PCA0H

PCA0L

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C8051F124/5/6/7

25.3.

Register Descriptions for PCA0

Following are detailed descriptions of the special function registers related to the operation of PCA0.

Bit7:

CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the
Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF
interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by
software.

Bit6:

CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.

Bit5:

CCF5: PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

Bit4:

CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

Bit3:

CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

Bit2:

CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

Bit1:

CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

Bit0:

CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, set-
ting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automati-
cally cleared by hardware and must be cleared by software.

R/W

Reset Value

CCF5

CCF4

CCF3

CCF2

CCF1

CCF0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xD8
0

Figure 25.10. PCA0CN: PCA Control Register

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C8051F124/5/6/7

Figure 25.11. PCA0MD: PCA0 Mode Register

Bit7:

CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.

Bits6-4:

UNUSED. Read = 000b, Write = don't care.

Bits3-1:

CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter

Bit0:

ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.

R/W

Reset Value

CIDL

CPS2

CPS1

CPS0

ECF

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

SFR Page:

0xD9
0

CPS2

CPS1

CPS0

Timebase

System clock divided by 12

System clock divided by 4

Timer 0 overflow

High-to-low transitions on ECI(max rate = system clock divided
by 4)

System clock

External clock divided by 8 (synchronized with system clock)

Reserved

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C8051F124/5/6/7

Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers

Bit7:

PWM16n: 16-bit Pulse Width Modulation Enable
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.

Bit6:

ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA0 module n.
0: Disabled.
1: Enabled.

Bit5:

CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA0 module n.
0: Disabled.
1: Enabled.

Bit4:

CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA0 module n.
0: Disabled.
1: Enabled.

Bit3:

MATn: Match Function Enable.
This bit enables/disables the match function for PCA0 module n. When enabled, matches of the
PCA0 counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to
be set to logic 1.
0: Disabled.
1: Enabled.

Bit2:

TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA0 module n. When enabled, matches of the
PCA0 counter with a module's capture/compare register cause the logic level on the CEXn pin to tog-
gle. If the PWMn bit is also set to logic 1, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.

Bit1:

PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA0 module n. When enabled, a pulse width modu-
lated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is logic 0; 16-bit mode is used
if PWM16n logic 1. If the TOGn bit is also set, the module operates in Frequency Output Mode.
0: Disabled.
1: Enabled.

Bit0:

ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.

R/W

Reset Value

PWM16n

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC, PCA0CPM3: 0xDD, PCA0CPM4: 0xDE, PCA0CPM5: 0xDF

SFR Page: PCA0CPM0: page 0, PCA0CPM1: page 0, PCA0CPM2: page 0, PCA0CPM3: 0, PCA0CPM4: page 0, PCA0CPM5: page 0

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C8051F124/5/6/7

Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte

Bits7-0:

PCA0CPLn: PCA0 Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: PCA0CPL0: 0xFB, PCA0CPL1: 0xFD, PCA0CPL2: 0xE9, PCA0CPL3: 0xEB, PCA0CPL4: 0xED, PCA0CPL5: 0xE1

SFR Page:

PCA0CPL0: page 0, PCA0CPL1: page 0, PCA0CPL2: page 0, PCA0CPL3: page 0, PCA0CPL4: page 0, PCA0CPL5: page 0

Bits7-0:

PCA0CPHn: PCA0 Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: PCA0CPH0: 0xFC, PCA0CPH1: 0xFD, PCA0CPH2: 0xEA, PCA0CPH3: 0xEC, PCA0CPH4: 0xEE, PCA0CPH5: 0xE2

SFR Page: PCA0CPH0: page 0, PCA0CPH1: page 0, PCA0CPH2: page 0, PCA0CPH3: page 0, PCA0CPH4: page 0, PCA0CPH5: page 0

Figure 25.16. PCA0CPHn: PCA0 Capture Module High Byte

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C8051F124/5/6/7

26.

JTAG (IEEE 1149.1)

Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE
1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan
Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test
Access Port and Operation of the IEEE 1149.1 specification.

The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.

Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 26.1 can be com-
manded. There are three DR's associated with JTAG Boundary-Scan, and four associated with Flash read/write oper-
ations on the MCU.

Figure 26.1. IR: JTAG Instruction Register

Reset Value

0x0000

Bit15

Bit0

IR Value

Instruction

Description

0x0000

EXTEST

Selects the Boundary Data Register for control and observability of all device pins

0x0002

SAMPLE/

PRELOAD

Selects the Boundary Data Register for observability and presetting the scan-path
latches

0x0004

IDCODE

Selects device ID Register

0xFFFF

BYPASS

Selects Bypass Data Register

0x0082

Flash Control

Selects FLASHCON Register to control how the interface logic responds to reads
and writes to the FLASHDAT Register

0x0083

Flash Data

Selects FLASHDAT Register for reads and writes to the Flash memory

0x0084

Flash Address

Selects FLASHADR Register which holds the address of all Flash read, write, and
erase operations

0x0085

Flash Scale

Selects FLASHSCL Register which controls the Flash one-shot timer and read-
always enable

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C8051F124/5/6/7

26.1.

Boundary Scan

The DR in the Boundary Scan path is an 134-bit shift register. The Boundary DR provides control and observability
of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands.

Table 26.1. Boundary Data Register Bit Definitions

EXTEST provides access to both capture and update actions, while Sample only performs a capture.

Bit

Action

Target

Capture

Reset Enable from MCU (C8051F121/3/5/7 devices)

Update

Reset Enable to /RST pin (C8051F121/3/5/7 devices)

Capture

Reset input from /RST pin (C8051F121/3/5/7 devices)

Update

Reset output to /RST pin (C8051F121/3/5/7 devices)

Capture

Reset Enable from MCU (C8051F120/2/4/6 devices)

Update

Reset Enable to /RST pin (C8051F120/2/4/6 devices)

Capture

Reset input from /RST pin (C8051F120/2/4/6 devices)

Update

Reset output to /RST pin (C8051F120/2/4/6 devices)

Capture

External Clock from XTAL1 pin

Update

Not used

Capture

Weak pullup enable from MCU

Update

Weak pullup enable to Port Pins

6, 8, 10, 12, 14, 16,

18, 20

Capture

P0.n output enable from MCU (e.g. Bit6=P0.0, Bit8=P0.1, etc.)

Update

P0.n output enable to pin (e.g. Bit6=P0.0oe, Bit8=P0.1oe, etc.)

7, 9, 11, 13, 15, 17,

19, 21

Capture

P0.n input from pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)

Update

P0.n output to pin (e.g. Bit7=P0.0, Bit9=P0.1, etc.)

22, 24, 26, 28, 30,

32, 34, 36

Capture

P1.n output enable from MCU

Update

P1.n output enable to pin

23, 25, 27, 29, 31,

33, 35, 37

Capture

P1.n input from pin

Update

P1.n output to pin

38, 40, 42, 44, 46,

48, 50, 52

Capture

P2.n output enable from MCU

Update

P2.n output enable to pin

39, 41, 43, 45, 47,

49, 51, 53

Capture

P2.n input from pin

Update

P2.n output to pin

54, 56, 58, 60, 62,

64, 66, 68

Capture

P3.n output enable from MCU

Update

P3.n output enable to pin

55, 57, 59, 61, 63,

65, 67, 69

Capture

P3.n input from pin

Update

P3.n output to pin

70, 72, 74, 76, 78,

80, 82, 84

Capture

P4.n output enable from MCU

Update

P4.n output enable to pin

71, 73, 75, 77, 79,

81, 83, 85

Capture

P4.n input from pin

Update

P4.n output to pin

86, 88, 90, 92, 94,

96, 98, 100

Capture

P5.n output enable from MCU

Update

P5.n output enable to pin

87, 89, 91, 93, 95,

97, 99, 101

Capture

P5.n input from pin

Update

P5.n output to pin

102, 104, 106, 108,

110, 112, 114, 116

Capture

P6.n output enable from MCU

Update

P6.n output enable to pin

103, 105, 107, 109,

111, 113, 115, 117

Capture

P6.n input from pin

Update

P6.n output to pin

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C8051F124/5/6/7

26.1.1. EXTEST Instruction

The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the
device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.

26.1.2. SAMPLE Instruction

The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the scan-
path latches.

26.1.3. BYPASS Instruction

The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data register.

26.1.4. IDCODE Instruction

The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.

Bit

Action

Target

118, 120, 122, 124,

126, 128, 130, 132

Capture

P7.n output enable from MCU

Update

P7.n output enable to pin

119, 121, 123, 125,

127, 129, 131, 133

Capture

P7.n input from pin

Update

P7.n output to pin

Table 26.1. Boundary Data Register Bit Definitions

Figure 26.2. DEVICEID: JTAG Device ID Register

Version = 0000b

Part Number = 0000 0000 0000 0111b (C8051F120/1/2/3/4/5/6/7)

Manufacturer ID = 0010 0100 001b (Cygnal Integrated Products)

Reset Value

Version

Part Number

Manufacturer ID

0xn0003243

Bit31

Bit28 Bit27

Bit12 Bit11

Bit1

Bit0

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C8051F120/1/2/3
C8051F124/5/6/7

26.2.

Flash Programming Commands

The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash
Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register.
Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the
IR register. Each read or write is then initiated by writing the appropriate Indirect Operation Code (IndOpCode) to the
selected data register. Incoming commands to this register have the following format:

IndOpCode: These bit set the operation to perform according to the following table:

The Poll operation is used to check the Busy bit as described below. Although a Capture-DR is performed, no
Update-DR is allowed for the Poll operation. Since updates are disabled, polling can be accomplished by shifting in/
out a single bit.

The Read operation initiates a read from the register addressed by the DRAddress. Reads can be initiated by shifting
only 2 bits into the indirect register. After the read operation is initiated, polling of the Busy bit must be performed to
determine when the operation is complete.

The write operation initiates a write of WriteData to the register addressed by DRAddress. Registers of any width up
to 18 bits can be written. If the register to be written contains fewer than 18 bits, the data in WriteData should be left-
justified, i.e. its MSB should occupy bit 17 above. This allows shorter registers to be written in fewer JTAG clock
cycles. For example, an 8-bit register could be written by shifting only 10 bits. After a Write is initiated, the Busy bit
should be polled to determine when the next operation can be initiated. The contents of the Instruction Register
should not be altered while either a read or write operation is busy.

Outgoing data from the indirect Data Register has the following format:

The Busy bit indicates that the current operation is not complete. It goes high when an operation is initiated and
returns low when complete. Read and Write commands are ignored while Busy is high. In fact, if polling for Busy to
be low will be followed by another read or write operation, JTAG writes of the next operation can be made while
checking for Busy to be low. They will be ignored until Busy is read low, at which time the new operation will ini-
tiate. This bit is placed ate bit 0 to allow polling by single-bit shifts. When waiting for a Read to complete and Busy is
0, the following 18 bits can be shifted out to obtain the resulting data. ReadData is always right-justified. This allows
registers shorter than 18 bits to be read using a reduced number of shifts. For example, the results from a byte-read
requires 9 bit shifts (Busy + 8 bits).

19:18

17:0

IndOpCode

WriteData

IndOpCode

Operation

Poll

Read

Write

18:1

ReadData

Busy

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C8051F124/5/6/7

Figure 26.3. FLASHCON: JTAG Flash Control Register

This register determines how the Flash interface logic will respond to reads and writes to the FLASHDAT
Register.

Bit7:

SFLE: Scratchpad FLASH Memory Access Enable
When this bit is set, FLASH reads and writes are directed to the two 128-byte Scratchpad FLASH
sectors. When SFLE is set to logic 1, FLASH accesses out of the address range 0x00-0xFF should not
be attempted (with the exception of address 0x400, which can be used to simultaneously erase both
Scratchpad areas). Reads/Writes out of this range will yield undefined results.
0: FLASH access directed to the 128k byte Program/Data FLASH sector.
1: FLASH access directed to the two 128 byte Scratchpad sectors.

Bits6-4:

WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASHDAT
Register per the following values:
000:

A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise ignored.

001:

A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.

010:

A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing
the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x1FBFE - 0x1FBFF, the entire user space
will be erased (i.e. entire Flash memory except for Reserved area 0x1FC00 - 0x1FFFF).

(All other values for WRMD2-0 are reserved.)

Bits3-0:

RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads from the FLASHDAT
Register per the following values:
0000:

A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise ignored.

0001:

A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no
operation is currently active. This mode is used for block reads.

Reset Value

SFLE

WRMD2

WRMD1

WRMD0

RDMD3

RDMD2

RDMD1

RDMD0

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

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C8051F124/5/6/7

26.3.

Debug Support

Each MCU has on-chip JTAG and debug logic that provides non-intrusive, full speed, in-circuit debug support using
the production part installed in the end application, via the four pin JTAG I/F. Cygnal's debug system supports inspec-
tion and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program
memory, or communications channels are required. All the digital and analog peripherals are functional and work
correctly (remain synchronized) while debugging. The Watchdog Timer (WDT) is disabled when the MCU is halted
during single stepping or at a breakpoint.

The C8051F120DK is a development kit with all the hardware and software necessary to develop application code
and perform in-circuit debug with the C8051F12x family. Each kit includes an Integrated Development Environment
(IDE) which has a debugger and integrated 8051 assembler. The kit also includes an RS-232 to JTAG interface mod-
ule referred to as the Serial Adapter. There is also a target application board with a C8051F120 installed. RS-232 and
JTAG cables and wall-mount power supply are also included.

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C8051F120/1/2/3
C8051F124/5/6/7

Disclaimers

Life support: These products are not designed for use in life support appliances or systems where malfunction of
these products can reasonably be expected to result in personal injury. Cygnal Integrated Products customers using or
selling these products for use in such applications do so at their own risk and agree to fully indemnify Cygnal Inte-
grated Products for any damages resulting from such applications.

Right to make changes: Cygnal Integrated Products reserves the right to make changes, without notice, in the prod-
ucts, including circuits and/or software, described or contained herein in order to improve design and/or performance.
Cygnal Integrated Products assumes no responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these products, and makes no representations or
warranties that these products are free from patent, copyright, or mask work infringement, unless otherwise specified.

CYGNAL INTEGRATED PRODUCTS

4301 Westbank Drive

Suite B-100

Austin, TX 78746

www.cygnal.com

CIP-51 is a trademark of Cygnal Integrated Products, Inc.
MCS-51 and SMBus are trademarks of Intel Corporation.
SPIis a trademark of Motorola, Inc.

C is a trademark of Philips Semiconductor.

Document Outline

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Document Outline

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